TMS320DM365
www.ti.com
SPRS457C–MARCH 2009–REVISED APRIL 2010
TMS320DM365
Digital Media System-on-Chip (DMSoC)
Check for Samples: TMS320DM365
1 TMS320DM365 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
MAC
• Highlights
– ARM® Javelle® Technology
– Embedded ICE-RT Logic for Real-Time
Debug
– High-Performance Digital Media
System-on-Chip (DMSoC)
– Up to 300-MHz ARM926EJ-S Clock Rate
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– Two Video Image Co-processors
(HDVICP, MJCP) Engines
– Supports a Range of Encode, Decode, and
Video Quality Operations
– Video Processing Subsystem
– 16K-Byte ROM
•
•
•
HW Face Detect Engine
Resize Engine from 1/16x to 8x
16-Bit Parallel AFE (Analog Front-End)
Interface Up to 120 MHz
4:2:2 (8-/16-bit) Interface
– Little Endian
• Two Video Image Co-processors
(HDVICP, MJCP) Engines
– Support a Range of Encode and Decode
Operations
– H.264, MPEG4, MPEG2, MJPEG, JPEG,
WMV9/VC1
•
•
•
3 DACs for HD Analog Video Output
Hardware On-Screen Display (OSD)
• Video Processing Subsystem
– Front End Provides:
– Capable of 720p 30fps H.264 video
processing
– Peripherals include EMAC, USB 2.0 OTG,
DDR2/NAND, 5 SPIs, 2 UARTs, 2
MMC/SD/SDIO, Key Scan
•
•
HW Face Detect Engine
Hardware IPIPE for Real-Time Image
Processing
– 8 Different Boot Modes and Configurable
Power-Saving Modes
– Pin-to-pin and software compatible with
DM368
– Extended temperature (-40ºC – 85ºC)
available for 300-Mhz device
– 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
– Debug Interface Support
–
Resize Engine
–
–
Resize Images From 1/16x to 8x
Separate Horizontal/Vertical
Control
–
Two Simultaneous Output Paths
•
•
IPIPE Interface (IPIPEIF)
Image Sensor Interface (ISIF) and CMOS
Imager Interface
16-Bit Parallel AFE (Analog Front End)
Interface Up to 120 MHz
Glueless Interface to Common Video
Decoders
– 338-Pin Ball Grid Array at 65nm Process
Technology
•
•
•
• High-Performance Digital Media
System-on-Chip (DMSoC)
– 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
– Fully Software-Compatible With ARM9™
BT.601/BT.656/BT.1120 Digital YCbCr
4:2:2 (8-/16-Bit) Interface
– Extended temperature available for 300-Mhz
device
• ARM926EJ-S™ Core
•
•
•
Histogram Module
Lens distortion correction module (LDC)
Hardware 3A statistics collection module
(H3A)
– Support for 32-Bit and 16-Bit
(Thumb® Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle
– Back End Provides:
1
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2
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