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THS1207IDAG4

更新时间： 2024-01-15 14:51:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
32页 318K
描述
4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32, GREEN, PLASTIC, TSSOP-32

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THS1207IDAG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.44
Is Samacsys：N最大模拟输入电压：4.05 V
最小模拟输入电压：1.4 V转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：R-PDSO-G32JESD-609代码：e4
长度：11 mm最大线性误差 (EL)：0.0366%
湿度敏感等级：2模拟输入通道数量：4
位数：12功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C输出位码：BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP32,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3/5,5 V
认证状态：Not Qualified采样速率：6 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：1.2 mm
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

THS1207IDAG4 数据手册

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www.ti.com  
TERMINAL  
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ  
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002  
Terminal Functions  
I/O  
DESCRIPTION  
NAME  
NO.  
32  
AINP  
AINM  
BINP  
BINM  
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog input, single-ended or positive input of differential channel A  
Analog input, single-ended or negative input of differential channel A  
Analog input, single-ended or positive input of differential channel B  
Analog input, single-ended or negative input of differential channel B  
Analog supply voltage  
31  
30  
29  
AV  
DD  
23  
24  
7
AGND  
BV  
Analog ground  
Digital supply voltage for buffer  
DD  
BGND  
CONV_CLK  
CS0  
8
Digital ground for buffer  
15  
22  
21  
17  
18  
Digital input. This input is the conversion clock input.  
Chip select input (active low)  
CS1  
Chip select input (active high)  
DGND  
Digital ground. Ground reference for digital circuitry.  
Digital supply voltage  
DV  
DD  
D0 – D9  
D10/RA0  
D11/RA1  
REFIN  
1–6,  
9–12  
I/O/Z Digital input, output; D0 = LSB  
13  
14  
28  
26  
I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is  
required for writing to the control register 0 and control register 1. See Table 7.  
I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register.  
This is required for writing to control register 0 and control register 1. See Table 7.  
I
Common-modereference input for the analog input channels. It is recommended that this pin be connected to the  
reference output REFOUT.  
REFP  
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.  
An external reference voltage at this input can be applied. This option can be programmed through control  
register 0. See Table 8.  
REFM  
25  
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.  
An external reference voltage at this input can be applied. This option can be programmed through control  
register 0. See Table 8.  
REFOUT  
27  
19  
16  
20  
O
I
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output  
requires a capacitor of 10 µF to AGND for filtering and stability.  
(1)  
RD  
The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active  
low as a data read select from the processor. See timing section.  
SYNC  
O
I
Synchronizationoutput. This signal indicates in a multichannel operation that data of channel A is brought to the  
digital output and can therefore be used for synchronization.  
(1)  
WR (R/W)  
This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only  
input WR, which is active low and used as data write select from the processor. In this case, the RD input is used  
as a read input from the processor. See timing section.  
(1)  
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.  
5
12345678...32

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