THC63LVDR84C_Rev.1.20_E
Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RC3
RD6
RC4
GND
RC5
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
RC6
RD0
LVDS GND
RA-
RA+
RB-
RB+
LVDS VCC
LVDS GND
RC-
RC+
RCLK-
RCLK+
RD-
RD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
Figure 2. Pin Diagram
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
Pin #
10, 9
12, 11
16, 15
20, 19
Direction
Type
Description
LVDS Data Inputs
Input
LVDS
RCLK+,
RCLK-
18, 17
LVDS Clock Inputs
Pixel Data Outputs
RA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
Output
Input
LVCMOS
Pixel Clock Output
H : Normal Operation
L : Power Down (All outputs are pulled to
ground)
/PDWN
25
Power Supply Pins for LVCMOS outputs
and digital circuitry
Ground Pins for LVCMOS outputs and
digital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry
VCC
GND
31, 40, 48, 56
4, 28, 36, 44, 52
-
Power
LVDS VCC
LVDS GND
PLL VCC
13
8, 14, 21
23
PLL GND
22, 24
Table 1. Pin Description
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2
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