Datasheet > THC63LVDR84C

THC63LVDR84C

更新时间： 2022-02-26 13:11:55

品牌	Logo	应用领域
THINE		/
页数	文件大小	规格书
15页	456K
描述
24bit Color LVDS Receiver

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数据手册

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THC63LVDR84C 数据手册

THC63LVDR84C_Rev.1.20_E

Switching Characteristics

Over recommended operating supply and temperature range unless otherwise specified

Symbol

t_RCP

t_RCH

t_RCL

t_RCD

Parameter

RCLK and CLKOUT Transition Time

LVCMOS CLKOUT High Time

LVCMOS CLKOUT Low Time

RCLK IN to CLKOUT Delay

Min

8.92

Typ*

T/2

Max

125

Unit

T/2

(3/14+3)×T

t_RS

t_RH

t_TLH

t_THL

LVCMOS Data Setup to CLKOUT

LVCMOS Data Hold from CLKOUT

LVCMOS Low to High Transition Time

LVCMOS High to Low Transition Time

0.35×T - 0.3

0.45×T - 1.6

0.7

1.0

0.55

0.25

PCLK=65MHz

PCLK=112MHz

-0.55

-0.25

t_SK

LVDS Receiver Skew Margin

t_RIP1

t_RIP0

t_RIP6

t_RIP5

t_RIP4

t_RIP3

t_RIP2

t_RPLL

LVDS Input Data Position0

LVDS Input Data Position1

LVDS Input Data Position2

LVDS Input Data Position3

LVDS Input Data Position4

LVDS Input Data Position5

LVDS Input Data Position6

Phase Lock Loop Set

- t_SK

0.0

T/7

2T/7

3T/7

4T/7

5T/7

6T/7

+ t_SK

T/7- t_SK

2T/7- t_SK

3T/7- t_SK

4T/7- t_SK

5T/7- t_SK

6T/7- t_SK

T/7+ t_SK

2T/7+ t_SK

3T/7+ t_SK

4T/7+ t_SK

5T/7+ t_SK

6T/7+ t_SK

10.0

*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC

Table 8. LVCMOS & LVDS Receiver AC Specifications

THine Electronics, Inc.

Security E

1...4 5 678 9 10...15

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