Datasheet > TH74KA22BVWKRNG

TH74KA22BVWKRNG

更新时间： 2023-01-03 10:46:52

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
20页	1116K
描述
Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84

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数据手册

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TH74KA22BVWKRNG 数据手册

TH7422B

PIN DESCRIPTION

Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.

This is the preload injection stage electrical input. Each Φ

pulse down overfills preload storage capacitance with

electrons. Φ

is connected to a diode cathode which anode is internally tied to Vss.

This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance

will be biased. Thus it drives preload level.

GL1

GL2

This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while V

deter-

GL1

mines its top level. Preload capacitance thus is charged up proportionately to (V

- V

) bias difference.

GL2

GL1

This is the main register storage grid clock. Charges are stored under Φ

when transfer is disabled (RE at low le-

vel). Φ is also used for lateral transfers to input nodes.

This is the main register transfer grid clock. Φ is used to isolate Φ content during lateral transfers. The main re-

gister is beginning and ending with Φ

which therefore controls main register access and outputs. Φ

is gated by

RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating

each Φ well.

This is the “Read Enable” input. When high, it allows Φ

input connection to main register, when low, main register

corresponding grids are pulled down whatever Φ

This input helps to serially read out two or more multiplexors with one single Φ

input level is.

signal for all. Data are stored into

the main register as long as RE is low, thus read out can occur later on.

This is the lateral transfer grid command. Lateral transfer is allowed when Φ is at high level. Φ is common to all

input nodes, all photodiode information is collected at the same time.

This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same

from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading

to overcrossing V

level are skimmed back into Φ main register wells.

This is the InGaAs photodiode common cathode bias. V is available on odd and even side, however, both pins are

connected together, to photodiode substrate.

This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges

to be read out when Φ is at low level.

5/20

1 2 3 456 7 8...20

中文翻译

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与TH74KA22BVWKRNG相关器件

型号	品牌	获取价格	描述	数据表
TH74KA22BVWKRNGS	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKRPGS	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSGB/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSGD/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSNG	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSNGB/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSNGD/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSPG	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSPGB/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84
TH74KA22BVWKSPGD/T	ATMEL	获取价格	Analog Circuit, 1 Func, CQCC84, WINDOWED, CERAMIC, J LEAD PACKAGE-84

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