Datasheet > TFRA84J13DS1

TFRA84J13DS1

更新时间： 2024-01-06 11:38:53

品牌	Logo	应用领域
杰尔 - AGERE		/
页数	文件大小	规格书
14页	237K
描述
Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0

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TFRA84J13DS1 数据手册

Product Description, Revision 4

April 29, 2005

TFRA84J13 Ultraframer

DS3/E3/DS2/E2/DS1/E1/DS0

1 Introduction

The documentation package for the TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 chip consists of the following

documents:

ꢀ The Ultramapper™ Family Register Description and the Ultramapper Family System Design Guide. These documents

are available on a password protected website.

ꢀ The Ultraframer Product Description (this document) and the Ultraframer Hardware Design Guide. These documents

are available on the public website shown below.

To contact Agere, please see the last page of this document.

To access related documents, including the documents mentioned above, please go to the following public website, or

contact your Agere representative:

http://www.agere.com/telecom/mappers_muxes.html

THSC

Framer CLK

CHI/PSB

Rx/Tx Clocks and Sync

MPU IF

FRM

MPU

x84/x63

DS1/J1/E1

FRM PLL IF

System

Interfaces

(x3)

M13/E13

MUX

(x3) DS3/E3

E2AISCLK/

DS2AISCLK

(x3) NSMI

(framer)

MRXC

DS1/J1/E1

DS2/E2

DS3/E3

380

Shared Low Speed I/O

Miscellaneous

TPG/TPM

Switching modes:

8PSB (x16)- x84/X63 DS1/J1/E1

x2016 DS0/E0

4CHI (x18) - x2016 DS0/E0

x84/x63

DS1/E1

Transport modes:

4DS1/J1/E1 (x86) -x84/x63 + prot.

4DS2/E2 (X86) – x63/x36 + prot.

DJA

JTAG

DS1XCLK,

E1XCLK

JTAG IF

Power and GND pins not shown

10/10/02

Figure 1-1. Ultraframer Block Diagram and High-Level Interface Definition

12 3 4 5 6 7...14

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