TC9400/9401/9402
input is balanced out by fixed charges from the refer-
ence voltage. As the input voltage is increased, the
number of reference pulses required to maintain bal-
ance increases, which causes the output frequency to
also increase. Since each charge increment is fixed, the
increase in frequency with voltage is linear. In addition,
the accuracy of the output pulse width does not directly
affect the linearity of the V/F. The pulse must simply be
long enough for full charge transfer to take place.
3.0
3.1
DETAILED DESCRIPTION
Voltage-to-Frequency (V/F) Circuit
Description
The TC9400 V/F converter operates on the principal of
charge balancing. The operation of the TC9400 is eas-
ily understood by referring to Figure 3-1. The input volt-
age (V ) is converted to a current (I ) by the input
IN
IN
resistor. This current is then converted to a charge on
the integrating capacitor and shows up as a linearly
decreasing voltage at the output of the Op Amp. The
lower limit of the output swing is set by the threshold
detector, which causes the reference voltage to be
applied to the reference capacitor for a time period long
enough to charge the capacitor to the reference volt-
age. This action reduces the charge on the integrating
The TC9400 contains a "self-start" circuit to ensure the
V/F converter always operates properly when power is
first applied. In the event that, during power-on, the Op
Amp output is below the threshold and C
is already
REF
charged, a positive voltage step will not occur. The Op
Amp output will continue to decrease until it crosses the
-3.0V threshold of the "self-start" comparator. When
this happens, an internal resistor is connected to the
Op Amp input, which forces the output to go positive
until the TC9400 is in its Normal Operating mode.
capacitor by a fixed amount (q = C
x V
), causing
REF
REF
the Op Amp output to step up a finite amount.
At the end of the charging period, C is shorted out.
REF
The TC9400 utilizes low power CMOS processing for
low input bias and offset currents, with very low power
dissipation. The open drain N-channel output FETs
provide high voltage and high current sink capability.
This dissipates the charge stored on the reference
capacitor, so that when the output again crosses zero,
the system is ready to recycle. In this manner, the con-
tinued discharging of the integrating capacitor by the
FIGURE 3-1:
10Hz TO 10kHz V/F CONVERTER
+5V
+
5V
14
V
R
10kΩ
L
DD
F
Threshold
OUT
8
11
Detect
3µsec
Delay
+
5V
Threshold
Detector
R
10kΩ
L
F
/2
OUT
10
9
Self-
Start
÷2
-3V
12 AMP OUT
Output
Common
V
OUT
REF
5
20kΩ
C
INT
820pF
TC9400
TC9401
TC9402
C
180pF
REF
12pF
R
IN
1MΩ
INPUT
60pF
I
IN
3
V
IN
–
+5V
Op Amp
+
Zero Adjust
0V –10V
50kΩ
510kΩ
2
V
V
7
I
GND
6
SS
REF
BIAS
-5V
Offset
1
4
10kΩ
R
Adjust
BIAS
100kΩ
Reference Voltage
(Typically -5V)
-5V
2002 Microchip Technology Inc.
DS21483B-page 7