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TC74HC390AP_07 PDF预览

TC74HC390AP_07

更新时间: 2024-01-14 10:11:47
品牌 Logo 应用领域
东芝 - TOSHIBA 计数器
页数 文件大小 规格书
11页 409K
描述
CMOS Digital Integrated Circuit Silicon Monolithic Dual Decade Counter

TC74HC390AP_07 数据手册

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TC74HC390AP/AF/AFN  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC390AP,TC74HC390AF,TC74HC390AFN  
Dual Decade Counter  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74HC390A is a high speed CMOS DUAL DECADE  
COUNTER fabricated with silicon gate C2MOS technology.  
TC74HC390AP  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
It consists of two independent 4-bit counters, each composed of  
a divide-by-two and a divide-by-five counter. The divide-by-two  
counter is incremented on the negative going transition of clock A  
(CKA ). The divided-by-five counter is incremented on the  
negative going transition of clock B (CKB ). The counter can be  
cascaded to form decade, bi-quinary, or various combinations up  
to a divide-by-100 counter. When the CLR input is set high, the  
Q outputs are set to low independent of the clock inputs.  
TC74HC390AF  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
High speed: f  
= 84 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
TC74HC390AFN  
Output drive capability: 10 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 4 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2~6 V  
CC  
Pin and function compatible with 74LS390  
Pin Assignment  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
1
2007-10-01  

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