T89C51RB2/RC2
8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
1. Description
T89C51RB2/RC2 is a high performance FLASH version Pinout is the standard 40/44 pins of the C52.
of the 80C51 8-bit microcontrollers. It contains a 16K
The fully static design of the T89C51RB2/RC2 allows
or 32Kbytes Flash memory block for program and data.
to reduce system power consumption by bringing the
The 16 Kbytes or 32 Kbytes FLASH memory can be clock frequency down to any value, even DC, without
programmed either in parallel mode or in serial mode loss of data.
with the ISP capability or with software. The
The T89C51RB2/RC2 has 2 software-selectable modes
programming voltage is internally generated from the
of reduced activity and 8 bit clock prescaler for further
standard V pin.
CC
reduction in power consumption. In the Idle mode the
The T89C51RB2/RC2 retains all features of the 80C52 CPU is frozen while the peripherals and the interrupt
with 256 bytes of internal RAM, a 7-source 4-level system are still operating. In the power-down mode the
interrupt controller and three timer/counters.
RAM is saved and all other functions are inoperative.
In addition, the T89C51RB2/RC2 has a Programmable The added features of the T89C51RB2/RC2 make it more
powerful for applications that need
pulse width
Counter Array, an XRAM of 1024 byte, a Hardware
Watchdog Timer, a Keyboard Interface, a SPI Interface,
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a speed
improvement mechanism (X2 mode).
2. Features
• 80C52 Compatible
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•
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•
•
•
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratch pad RAM
10 Interrupt sources with 4 priority levels
Dual Data Pointer
• On-chip 1024 bytes expanded RAM (XRAM)
•
Software selectable size (0, 256, 512, 768, 1024
bytes)
•
256 bytes selected at reset for TS87C51RB2/RC2
compatibility
• Keyboard interrupt interface on port P1
• SPI Interface (Master / Slave Mode)
• 8-bit clock prescaler
• Variable length MOVX for slow RAM/peripherals
• ISP (In System Programming) using standard V
CC
• Improved X2 mode with independant selection for
power supply.
CPU and each peripheral
• Boot ROM contains low level FLASH programming
• Programmable Counter Array 5 Channels with:
routines and a default serial loader
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•
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High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
• High-Speed Architecture
•
40 MHz in standard mode
•
20 MHz in X2 mode (6 clocks/machine cycle)
• 16K/32K bytes on-chip FLASH program / data
Memory
• Asynchronous port reset
•
•
Byte and page (128 bytes) erase and write
100k write cycles
• Full duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (inhibit ALE)
Rev. B - 30-Mar-01
1
Preliminary