Datasheet > T0502SK

T0502SK

更新时间： 2022-02-26 14:44:57

品牌	Logo	应用领域
竹懋 - CITC		/
页数	文件大小	规格书
6页	746K
描述
Ultra-Low Capacitance ESD Protection Device

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T0502SK 数据手册

T0502SK

Ultra-Low Capacitance ESD Protection Device

Chip Integration Technology Corporation

Application Information

Pin Connection in PCB

PCB Layout Guidelines

is capable to provide ESD protection for

two data lines simultaneously. The pin connevtion

is shown in Figure 1.

For optimum ESD protection and the whole circuit

performance, the following PCB layout guidelines are

recommended:

T0502SK

T0502SK GND pin to the PCB GND rail

path should be as short as possible. It could reduce

the ESD transient return path to GND .

The vias connecting T0502SK GND pins to PCB

GND should be wide.

Two parallel data lines, from inner IC to I/O port

connector, could connect to T0502SK two I/O pins

directly. Pin3 of T0502SK is the negative reference

pin, which should connect to the GND of PCB. The

connection wires should be as short as possible in

order to minimize the parasitic inductance.

I/O1

To Connector

I/O2

Place T0502SK as close to th connector port as

possible. It could reduce the parasitic inductance

and restrict ESD couplinginto adjacent traces.

Avoid running critical signals near board edges.

To Inner IC

Figure 2

Layout Guidelines

T0502SK

Figure 1 T0502SK pin connection in PCB

Universal Serial Bus ESD Protection

V_BUS

D+

V_BUS

R_T

USB

Controller

USB

Port

R_T

D-

GND

C_T

Figure 3 Schematic and Diagram for USB 2.0 Protection using T0502SK

Document ID : DS-22V06

Revised Date : 2016/08/29

Revision : C

1 2 345 6

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