List of figures
STM8S105xx
List of figures
Figure 1. STM8S105xx access line block diagram ................................................................................11
Figure 2. Flash memory organisation ....................................................................................................14
Figure 3. LQFP 48-pin pinout .................................................................................................................22
Figure 4. LQFP 44-pin pinout .................................................................................................................23
Figure 5. LQFP/VFQFPN/UFQFPN 32-pin pinout ................................................................................24
Figure 6. SDIP 32-pin pinout ..................................................................................................................25
Figure 7. Memory map ...........................................................................................................................29
Figure 8. Supply current measurement conditions ................................................................................58
Figure 9. Pin loading conditions .............................................................................................................59
Figure 10. Pin input voltage ...................................................................................................................59
Figure 11. fCPUmax versus VDD ..............................................................................................................63
Figure 12. External capacitor CEXT .......................................................................................................64
Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................73
Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................74
Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................74
Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................75
Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................75
Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................76
Figure 19. HSE external clocksource .....................................................................................................77
Figure 20. HSE oscillator circuit diagram ...............................................................................................78
Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................79
Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................80
Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................81
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................83
Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................84
Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................84
Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................86
Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................87
Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................87
Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................88
Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................88
Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................89
Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................89
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................90
Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................90
Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................91
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................92
Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................92
Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................93
Figure 40. Recommended reset pin protection ......................................................................................93
Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................95
Figure 42. SPI timing diagram - slave mode and CPHA = 1(1) .............................................................96
Figure 43. SPI timing diagram - master mode(1) ...................................................................................96
Figure 44. Typical application with I2C bus and timing diagram (1) .......................................................98
Figure 45. ADC accuracy characteristics .............................................................................................101
Figure 46. Typical application with ADC ..............................................................................................102
Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................106
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