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STM1403ASM-Q6F PDF预览

STM1403ASM-Q6F

更新时间: 2022-11-26 03:33:30
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 电池监控
页数 文件大小 规格书
9页 166K
描述
3V FIPS-140 Security Supervisor with Battery Switchover

STM1403ASM-Q6F 数据手册

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STM1403  
TAMPER DETECTION  
Physical  
Supply Voltage  
The internally switched supply voltage, V  
There are four (4) high-impedance physical  
tamper detect input pins, 2 normally set to High  
(NH) and 2 normally set to Low (NL). Each input is  
designed with a glitch immunity. These inputs can  
be connected externally to several types of actua-  
tor devices (e.g., switches, wire mesh). A tamper  
on any one of the four inputs that causes its state  
to change will trigger the security alarm (SAL) and  
drive it to active-low. Once the tamper condition no  
longer exists, the SAL will return to its normal High  
state.  
(ei-  
INT  
ther V input or V  
input) is continuously mon-  
CC  
BAT  
itored. If V  
should exceed the over voltage trip  
INT  
point, V (set at 4.2V, typical), or should go below  
HV  
the under voltage trip point, V (set at 2.0v, typi-  
LV  
cal). SAL will be driven active-low. Once the  
tamper condition no longer exists, the SAL pin will  
return to its normal High state.  
When no tamper condition exists, SAL is normally  
High.  
When a tamper is detected, the SAL is activated  
(driven low), independent of the part type. V  
can be driven to one of three states, depending on  
which variant of STM1403 is being used (see De-  
vice Options, page 1):  
TP and TP are set Normally to High (NH). They  
1
3
OUT  
are connected externally through a closed switch  
or a high-impedance resistor to V (in the case  
of STM1403A) or V  
C), A tamper condition will be detected when the  
input pin is pulled low. If not used, tie the pin to  
OUT  
(in the case of STM1403B/  
TPU  
ON;  
High-Z; or  
Ground (V ).  
V
or V  
.
OUT  
TPU  
SS  
TP and TP are set Normally to Low (NL). They  
2
4
are connected externally through a high-imped-  
Note: The STM1403 must be initially powered  
above V to enable the tamper detection  
ance resistor or a closed switch to V . A tamper  
SS  
RST  
condition will be detected when the input pin is  
alarms. For example, if the battery is on while V  
CC  
pulled high. If not used, tie the pin to V  
.
= 0V, no alarm condition can be detected until V  
SS  
CC  
rises above V  
(and t  
expires). From this  
rec  
RST  
point on, alarms can be detected either on battery  
or V . This is done to avoid false alarms when  
CC  
the device goes from no power to its operational  
state.  
5/9  

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