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STK17TA8RF35I PDF预览

STK17TA8RF35I

更新时间: 2024-02-23 16:22:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟双倍数据速率光电二极管外围集成电路
页数 文件大小 规格书
27页 284K
描述
REAL TIME CLOCK, PDSO48, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, PLASTIC, SSOP-48

STK17TA8RF35I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Contact Manufacturer零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknown风险等级:5.38
最大时钟频率:0.032 MHz外部数据总线宽度:8
信息访问方法:PARALLEL, DIRECT ADDRESSJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.88 mm
湿度敏感等级:3端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.79 mm最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.52 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

STK17TA8RF35I 数据手册

 浏览型号STK17TA8RF35I的Datasheet PDF文件第3页浏览型号STK17TA8RF35I的Datasheet PDF文件第4页浏览型号STK17TA8RF35I的Datasheet PDF文件第5页浏览型号STK17TA8RF35I的Datasheet PDF文件第7页浏览型号STK17TA8RF35I的Datasheet PDF文件第8页浏览型号STK17TA8RF35I的Datasheet PDF文件第9页 
STK17TA8  
SRAM READ CYCLES #1 & #2  
SYMBOLS  
STK17TA8-25  
STK17TA8-35  
STK17TA8-45  
NO.  
PARAMETER  
UNITS  
#1  
#2  
Alt.  
tACS  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
tELQV  
1
2
Chip Enable Access Time  
Read Cycle Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
c
c
tAVAV  
tAVAV  
tRC  
tAA  
tOE  
tOH  
tLZ  
25  
35  
45  
d
tAVQV  
3
Address Access Time  
25  
12  
35  
15  
45  
20  
tGLQV  
4
Output Enable to Data Valid  
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
d
tAXQX  
5
3
3
3
3
3
3
tELQX  
tEHQZ  
tGLQX  
6
e
tHZ  
tOLZ  
tOHZ  
tPA  
tPS  
7
10  
10  
25  
13  
13  
35  
15  
15  
45  
8
0
0
0
0
0
0
e
tGHQZ  
9
b
tELICC  
10  
b
tEHICC  
11  
Notes  
c:  
W
must be high during SRAM READ cycles  
and  
d: Device is continuously selected with  
E
G
both low  
e: Measured ± 200mV from steady state output voltage  
f: HSB must remain high during READ and WRITE cycles.  
SRAM READ CYCLE #1: Address Controlledc,d,f  
2
tAVAV  
ADDRESS  
3
tAVQV  
5
tAXQX  
DATA VALID  
DQ (DATA OUT)  
SRAM READ CYCLE #2: E Controlledc,f  
2
tAVAV  
ADDRESS  
1
tELQV  
11  
tEHICCL  
6
tELQX  
E
7
tEHQZ  
G
9
tGHQZ  
4
tGLQV  
8
tGLQX  
DQ (DATA OUT)  
DATA VALID  
10  
tELICCH  
ACTIVE  
STANDBY  
ICC  
September 2005  
6
Document Control #ML0025 rev 1.2  

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