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STA2062

更新时间: 2024-02-18 10:51:48
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器和处理器外围集成电路全球定位系统
页数 文件大小 规格书
5页 160K
描述
Cartesio⑩ Infotainment application processor with embedded GPS

STA2062 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:BGA针数:361
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.78Is Samacsys:N
JESD-609代码:e2湿度敏感等级:3
端子面层:Tin/Silver (Sn/Ag)Base Number Matches:1

STA2062 数据手册

 浏览型号STA2062的Datasheet PDF文件第2页浏览型号STA2062的Datasheet PDF文件第3页浏览型号STA2062的Datasheet PDF文件第4页浏览型号STA2062的Datasheet PDF文件第5页 
STA2062  
Cartesio™  
Infotainment application processor with embedded GPS  
Data Brief  
Features  
High performance ARM926 MCU (up to 333MHz)  
MCU memory organization  
– Cache: 16KByte instruction, 16KByte data  
8KByte instruction TCM (tightly coupled memory)  
– 8KByte data TCM  
LFBGA361 (16x16x1.4mm)  
– 32KByte embedded ROM for boot  
Two banks of 64KByte embedded SRAM  
– 512Byte embedded SRAM for back-up  
– 4GByte total linear address space  
– Memory extension through:  
Flexible static memory controller-FSMC  
(NOR/NAND Flash, CF/CF+, ROM, SRAM  
support)  
Four multichannel serial ports (MSP) with 32x8  
separate transmit and receive FIFO  
Color LCD controller for STN,TFT or HR-TFT panels  
USB 2.0 OTG high speed dual role controller  
(ULPI interface)  
USB full speed dual role controller with  
Mobile DDR/SDRAM controller:  
16bit data @166MHz, 2 Chip Select,  
512Kbit each  
integrated 1.1 physical layer transceiver  
Two secure-digital multimedia memory card  
Interface (SD/SDIO/MMC) up to 8 bit data  
Interrupt  
SPDIF input interface  
– 64-channel interrupt controller (VIC)  
– 16-vectorized interrupts with 16  
programmable priority Level  
C3 hardware Reed-Solomon decoder  
Hardware sample rate converter (SaRaC)  
Two controller area network (CAN)  
Four 32-bit GPIO ports  
JTAG based in-circuit emulator (ICE) with  
embedded medium trace module  
Typical working condition: V : 1.2 10ꢀV,  
DMA  
Two 8-channel double port system DMA  
controllers  
– 32 DMA request for each controller  
dd  
Two external DMA requests are supported  
V : 1.8V  
IO  
32 channel high performance GPS correlation  
embedded subsystem  
Eight 32-bit free running timers/counters  
Four 16-bit extended function timer (EFT) with  
input capture/output compare and PWM  
Real time clock (RTC)  
Overdrive: V : 1.4 5ꢀV, V : 1.8 10ꢀV,  
dd  
IO  
2.5 10ꢀV  
Bus frequency: 166 MHz (overdrive)  
Bus/DDR frequency: 166 MHz  
HCMOS 0.90µm process  
Package:  
Pulse width light modulator (PWL)  
32-bit watchdog timer  
– LFBGA16x16x1.4mm (19x19balls)  
– 0.8mm ball pitch, (0.4mm ball)  
– Full array  
Four autobaud UART with 64X8 transmit and 64x12  
receive FIFO with DMA and hardware flow control  
Ambient temperature range: -40 / +85°C  
One IrDA(SIR/MIR/FIR) interface  
Three I C multi-master/slave interfaces  
Two synchronous serial port (SSP) with 32x32  
separate transmit and receive FIFO with  
Motorola-SPI, National-MicroWire and Texas-  
SSI support modes  
2
Table 1.  
Order code  
STA2062  
Device summary  
Package  
Packing  
LFBGA361  
Tray  
October 2007  
Rev 2  
1/5  
For further information contact your local STMicroelectronics sales office.  
www.st.com  
5

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