TMS320C6474
www.ti.com
SPRS552H–OCTOBER 2008–REVISED APRIL 2011
TMS320C6474 Multicore Digital Signal Processor
1 Features
12
•
•
1.2-GHz Device: -40°C to 95°C(1)
1-GHz Device: -40°C to 100°C
• Key Features
– High-Performance Multicore DSP (C6474)
• 3 TMS320C64x+™ DSP Cores
– Dedicated SPLOOP Instructions
– Compact Instructions (16-Bit)
– Exception Handling
– Instruction Cycle Time: 0.83 ns (1.2-GHz
Device); 1 ns (1-GHz Device); 1.18 ns
(850-MHz Device)
– Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz
Device); 1 GHz (1-GHz Device); 850 MHz
(850-MHz Device)
– Commercial Temperature and Extended
Temperature
– 3 TMS320C64x+™ DSP Cores; Six RSAs for
CDMA Processing (2 per core)
– Enhanced VCP2/TCP2
– Frame Synchronization Interface
– 16-/32-Bit DDR2-667 Memory Controller
– EDMA3 Controller
• TMS320C64x+ Megamodule L1 Memory
Architecture
– 256 K-Bit (32 K-Byte) L1P Program Cache
[Direct Mapped]
– 256 K-Bit (32 K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 512 K-Bit (64 K-Byte) L3 ROM
• Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Antenna Interface
– Two 1x Serial RapidIO® Links, v1.2
– Supports up to Eight 2-Mbps 3 GPP
(6 Iterations)
• Endianness: Little Endian, Big Endian
• Frame Synchronization Interface
Compliant
– One 1.8-V Inter-Integrated Circuit (I2C) Bus
– Two 1.8-V McBSPs
– Time Alignment Between Internal
– 1000 Mbps Ethernet MAC (EMAC)
– Six 64-Bit General-Purpose Timers
– 16 General-Purpose I/O (GPIO) Pins
– Internal Semaphore Module
Subsystems, External Devices/System
– OBSAI RP1 Compliant for Frame Burst Data
– Alternate Interfaces for non-RP1 and
non-UMTS Systems
– System PLL and PLL Controller/DDR PLL
and PLL Controller, Dedicated to DDR2
Memory Controller
• 16-/32-Bit DDR2-667 Memory Controller
• EDMA3 Controller (64 Independent Channels)
• Antenna Interface
• High-Performance Multicore DSP (C6474)
– Instruction Cycle Time:
– 6 Configurable Links (Full Duplex)
– Supports OBSAI RP3 Protocol, v1.0:
768-Mbps, 1.536-, 3.072-Gbps Link Rates
– Supports CPRI Protocol V2.0: 614.4-Mbps,
•
•
•
1.2-GHz Device: 0.83-ns
1-GHz Device: 1-ns
850-MHz Device: 1.18 ns
1.2288-, 2.4576-Gbps Link Rates
– Clock Rate:
– Clock Input Independent or Shared with CPU
(Selectable at Boot-Time)
•
•
•
1.2-GHz Device: 1 GHz to 1.2 GHz
1-GHz Device: 1 GHz
850-MHz Device: 850 MHz
• Two 1x Serial RapidIO® Links, v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing and DirectIO Support
– Error Management Extensions and
Congestion Control
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• Two 1.8-V McBSPs
– Eight 32-Bit Instructions/Cycle
– Commercial Temperature:
•
•
1.2-GHz Device: 0°C to 95°C
850-MHZ and 1-GHz Device: 0°C to 100°C
– Extended Temperature:
(1)
Note: Advance Information is presented in this document for
the C6474 1.2-GHz extended temperature device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
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