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SNJ54AHCT367J PDF预览

SNJ54AHCT367J

更新时间： 2024-01-29 05:34:53
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
6页 102K
描述
HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SNJ54AHCT367J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：unknown风险等级：5.84
其他特性：ONE FUNCTION WITH TWO BITS控制类型：ENABLE LOW
系列：AHCT/VHCT/VTJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.008 A
位数：6功能数量：1
端口数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
电源：5 VProp。Delay @ Nom-Sup：7.5 ns
传播延迟（tpd）：7.5 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SNJ54AHCT367J 数据手册

 浏览型号SNJ54AHCT367J的Datasheet PDF文件第2页浏览型号SNJ54AHCT367J的Datasheet PDF文件第3页浏览型号SNJ54AHCT367J的Datasheet PDF文件第4页浏览型号SNJ54AHCT367J的Datasheet PDF文件第5页浏览型号SNJ54AHCT367J的Datasheet PDF文件第6页 
SN54AHCT367, SN74AHCT367  
HEX BUFFERS AND LINE DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS418F – JUNE 1998 – REVISED MAY 2002  
SN54AHCT367 . . . J OR W PACKAGE  
SN74AHCT367 . . . D, DB, DGV, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
True Outputs  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1OE  
1A1  
1Y1  
1A2  
1Y2  
1A3  
1Y3  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
2OE  
2A2  
2Y2  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
12 2A1  
– 1000-V Charged-Device Model (C101)  
11  
10  
9
2Y1  
1A4  
1Y4  
description  
The ’AHCT367 devices are designed specifically  
to improve both the performance and density of  
3-state memory address drivers, clock drivers,  
and bus-oriented receivers and transmitters.  
These devices are organized as dual 4-line  
and 2-line buffers/drivers with active-low  
output-enable (1OE and 2OE) inputs. When OE is  
low, the device passes noninverted data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
SN54AHCT367 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2A2  
2Y2  
NC  
1Y1  
1A2  
NC  
4
5
6
7
8
17  
16  
15 2A1  
14  
9 10 11 12 13  
1Y2  
1A3  
To ensure the high-impedance state during power  
2Y1  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74AHCT367N  
SN74AHCT367N  
Tube  
SN74AHCT367D  
AHCT367  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT367DR  
SN74AHCT367NSR  
SN74AHCT367DBR  
SN74AHCT367PWR  
–40°C to 85°C  
SOP – NS  
AHCT367  
HB367  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
CDIP – J  
HB367  
SN74AHCT367DGVR HB367  
SNJ54AHCT367J  
SNJ54AHCT367W  
SNJ54AHCT367FK  
SNJ54AHCT367J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT367W  
SNJ54AHCT367FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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