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SN75C189DBLE-00 PDF预览

SN75C189DBLE-00

更新时间： 2024-01-04 18:17:09
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
20页 735K
描述
LINE RECEIVER, PDSO14

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SN75C189DBLE-00 技术参数

生命周期：Obsolete包装说明：SSOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.13
Is Samacsys：N其他特性：RESPONSE CONTROL
输入特性：SCHMITT TRIGGER接口集成电路类型：LINE RECEIVER
接口标准：EIA-232-DJESD-30 代码：R-PDSO-G14
长度：6.2 mm功能数量：1
端子数量：14最高工作温度：70 °C
最低工作温度：输出特性：TOTEM-POLE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
最大接收延迟：6000 ns接收器位数：4
座面最大高度：2 mm最大压摆率：0.7 mA
最大供电电压：6 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

SN75C189DBLE-00 数据手册

 浏览型号SN75C189DBLE-00的Datasheet PDF文件第2页浏览型号SN75C189DBLE-00的Datasheet PDF文件第3页浏览型号SN75C189DBLE-00的Datasheet PDF文件第4页浏览型号SN75C189DBLE-00的Datasheet PDF文件第5页浏览型号SN75C189DBLE-00的Datasheet PDF文件第6页浏览型号SN75C189DBLE-00的Datasheet PDF文件第7页 
SN75C189, SN75C189A  
QUADRUPLE LOW-POWER LINE RECEIVERS  
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000  
D, DB, OR N PACKAGE  
(TOP VIEW)  
Meet or Exceed the Requirements of  
TIA/EIA-232-F and ITU Recommendation  
V.28  
1A  
1 CONT  
1Y  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
Low Supply Current . . . 420 µA Typ  
Preset On-Chip Input Noise Filter  
Built-in Input Hysteresis  
4A  
4 CONT  
4Y  
2A  
2 CONT  
2Y  
3A  
Response and Threshold Control Inputs  
Push-Pull Outputs  
3 CONT  
3Y  
GND  
8
Functionally Interchangeable and  
Pin-to-Pin Compatible With  
Texas Instruments SN75189/SN75189A and  
Motorola MC1489/MC1489A  
Package Options Include Plastic  
Small-Outline (D) and Shrink Small-Outline  
(DB) Packages, and Standard Plastic (N)  
DIP  
description  
TheSN75C189andSN75C189Aarelow-power, bipolar, quadruple line receivers that are used to interface data  
terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices have been designed  
to conform to TIA/EIA-232-F.  
The SN75C189 has a 0.33-V typical hysteresis, compared with 0.97 V for the SN75C189A. Each receiver has  
provision for adjustment of the overall input threshold levels. This is achieved by choosing external series  
resistors and voltages to provide bias levels for the response-control pins. The output is in the high logic state  
if the input is open circuit or shorted to ground.  
These devices have an on-chip filter that rejects input pulses of less than 1-µs duration. An external capacitor  
can be connected from the control pins to ground to provide further input noise filtering for each receiver.  
The SN75C189 and SN75C189A have been designed using low-power techniques in a bipolar technology. In  
most applications, these receivers interface to single inputs of peripheral devices such as UARTs, ACEs, or  
microprocessors. By using sampling, such peripheral devices usually are insensitive to the transition times of  
theinputsignals. Ifthisisnotthecase, orforotheruses, itisrecommendedthattheSN75C189andSN75C189A  
outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.  
The SN75C189 and SN75C189A are characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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