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SN74LS390DR2 PDF预览

SN74LS390DR2

更新时间： 2024-02-02 09:16:05
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 光电二极管
页数 文件大小 规格书
5页 71K
描述
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16, SOIC-16

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SN74LS390DR2 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.58计数方向：UP
系列：LSJESD-30 代码：R-PDSO-G16
长度：9.9 mm负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER工作模式：ASYNCHRONOUS
位数：4功能数量：2
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：60 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：NEGATIVE EDGE宽度：3.9 mm
最小 fmax：25 MHzBase Number Matches：1

SN74LS390DR2 数据手册

 浏览型号SN74LS390DR2的Datasheet PDF文件第1页浏览型号SN74LS390DR2的Datasheet PDF文件第3页浏览型号SN74LS390DR2的Datasheet PDF文件第4页浏览型号SN74LS390DR2的Datasheet PDF文件第5页 
SN54/74LS390 • SN54/74LS393  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
CP  
CP  
CP  
Clock (Active LOW going edge)  
Input to +16 (LS393)  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
1.0 U.L.  
Clock (Active LOW going edge)  
Input to ÷2 (LS390)  
0
1
Clock (Active LOW going edge)  
Input to ÷5 (LS390)  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
1.5 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
MR  
Q –Q  
0
Master Reset (Active HIGH) Input  
Flip-Flop outputs (Note b)  
3
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b) Temperature Ranges.  
FUNCTIONAL DESCRIPTION  
Each half of the SN54/74LS393 operates in the Modulo 16  
binary sequence, as indicated in the ÷16 Truth Table. The first  
flip-flop is triggered by HIGH-to-LOW transitions of the CP  
input signal. Each of the other flip-flops is triggered by a  
HIGH-to-LOW transition of the Q output of the preceding  
flip-flop. Thus state changes of the Q outputs do not occur  
simultaneously. This means that logic signals derived from  
combinations of these outputs will be subject to decoding  
spikes and, therefore, should not be used as clocks for other  
counters, registers or flip-flops. A HIGH signal on MR forces  
all outputs to the LOW state and prevents counting.  
section operates in 4.2.1 binary sequence, as shown in the ÷5  
Truth Table, with the third stage output exhibiting a 20% duty  
cycle when the input frequency is constant. To obtain a ÷10  
function having a 50% duty cycle output, connect the input  
signal to CP and connect the Q output to the CP input; the  
1
3
0
Q output provides the desired 50% duty cycle output. If the  
0
input frequency is connected to CP and the Q output is  
connected to CP , a decade divider operating in the 8.4.2.1  
1
0
0
BCD codeisobtained, asshownintheBCDTruthTable.Since  
the flip-flops change state asynchronously, logic signals  
derived from combinations of LS390 outputs are also subject  
to decoding spikes. A HIGH signal on MR forces all outputs  
LOW and prevents counting.  
Each half of the LS390 contains a ÷5 section that is  
independent except for the common MR function. The ÷5  
SN54/74LS390 LOGIC DIAGRAM (one half shown)  
CP  
1
0
CP  
K
CP  
J
K
CP  
J
K
CP  
J
K
CP  
J
C
C
C
C
D
D
D
D
Q
Q
Q
Q
MR  
Q
Q
Q
Q
3
0
1
2
SN54/74LS393 LOGIC DIAGRAM (one half shown)  
CP  
K
CP  
J
K
CP  
J
K
CP  
J
K
CP  
J
C
C
C
C
D
D
D
D
Q
Q
Q
Q
MR  
Q
Q
Q
Q
3
0
1
2
FAST AND LS TTL DATA  
5-2  
12345

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