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Datasheet > SN74HCT139N-00
SN74HCT139N-00 PDF预览

SN74HCT139N-00

更新时间： 2024-02-27 07:15:38
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件
页数 文件大小 规格书
14页 657K
描述
HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16

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SN74HCT139N-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.2
系列：HCTJESD-30 代码：R-PDIP-T16
长度：19.305 mm负载电容（CL）：50 pF
功能数量：2端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：43 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74HCT139N-00 数据手册

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SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003  
SN54HCT139 . . . J OR W PACKAGE  
SN74HCT139 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
1G  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Typical t = 10 ns  
pd  
4-mA Output Drive at 5 V  
2G  
2A  
2B  
1B  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
12 2Y0  
Designed Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
11  
10  
9
2Y1  
2Y2  
2Y3  
D
Incorporate Two Enable Inputs to Simplify  
Cascading and/or Data Reception  
SN54HCT139 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’HCT139 devices are designed for  
high-performance memory-decoding or  
3
2
1
20 19  
18  
2A  
2B  
NC  
1B  
1Y0  
NC  
4
5
6
7
8
data-routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, these decoders can minimize  
the effects of system decoding. When employed  
with high-speed memories utilizing a fast enable  
circuit, the delay time of these decoders and the  
enable time of the memory usually are less than  
the typical access time of the memory. This means  
that the effective system delay introduced by the  
decoders is negligible.  
17  
16  
15 2Y0  
14  
9 10 11 12 13  
1Y1  
1Y2  
2Y1  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HCT139N  
SN74HCT139N  
SN74HCT139D  
SN74HCT139DR  
SN74HCT139DT  
SN74HCT139DBR  
SN74HCT139PWR  
SN74HCT139PWT  
SNJ54HCT139J  
SNJ54HCT139W  
SNJ54HCT139FK  
HCT139  
−40°C to 85°C  
SSOP − DB  
HT139  
HT139  
TSSOP − PW  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT139J  
SNJ54HCT139W  
−55°C to 125°C  
SNJ54HCT139FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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