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SN74ALS163BNE4 PDF预览

SN74ALS163BNE4

更新时间： 2024-02-20 13:49:50
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
27页 689K
描述
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

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SN74ALS163BNE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：DIP
包装说明：ROHS COMPLIANT, PLASTIC, DIP-16针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.22
Is Samacsys：N其他特性：TCO OUTPUT
计数方向：UP系列：ALS
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：19.305 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：40000000 Hz最大I（ol）：0.008 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：21 mA传播延迟（tpd）：20 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Counters最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：40 MHzBase Number Matches：1

SN74ALS163BNE4 数据手册

 浏览型号SN74ALS163BNE4的Datasheet PDF文件第2页浏览型号SN74ALS163BNE4的Datasheet PDF文件第3页浏览型号SN74ALS163BNE4的Datasheet PDF文件第4页浏览型号SN74ALS163BNE4的Datasheet PDF文件第5页浏览型号SN74ALS163BNE4的Datasheet PDF文件第6页浏览型号SN74ALS163BNE4的Datasheet PDF文件第7页 
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163  
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163  
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS  
SDAS276A – DECEMBER 1994 – REVISED JULY 2000  
SN54ALS161B, SN54ALS162B, SN54ALS163B,  
Internal Look-Ahead Circuitry for Fast  
Counting  
SN54AS161, SN54AS163 . . . J PACKAGE  
SN74ALS161B, SN74AS161,  
Carry Output for n-Bit Cascading  
Synchronous Counting  
Synchronously Programmable  
SN74AS163 . . . D OR N PACKAGE  
SN74ALS163B . . . D, DB, OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Small-Outline (D) and Shrink Small-Outline  
(DB) Packages, Ceramic Chip Carriers (FK),  
Standard Plastic (N) and Ceramic (J) DIPs  
Q
A
B
C
D
Q
B
Q
C
description  
Q
D
ENT  
ENP  
GND  
These synchronous, presettable, 4-bit decade  
and binary counters feature an internal carry  
look-ahead circuitry for application in high-speed  
counting designs. The SN54ALS162B is a 4-bit  
decade counter. The ’ALS161B, ’ALS163B,  
’AS161, and ’AS163 devices are 4-bit binary  
counters. Synchronous operation is provided by  
having all flip-flops clocked simultaneously so that  
the outputs change coincidentally with each other  
when instructed by the count-enable (ENP, ENT)  
inputs and internal gating. This mode of operation  
eliminates the output counting spikes normally  
associated with asynchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock input waveform.  
LOAD  
SN54ALS161B, SN54ALS162B, SN54ALS163B,  
SN54AS161, SN54AS163 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
C
D
Q
D
9 10 11 12 13  
These counters are fully programmable; they can  
be preset to any number between 0 and 9 or 15.  
Because presetting is synchronous, setting up a  
low level at the load (LOAD) input disables the  
counter and causes the outputs to agree with the  
setup data after the next clock pulse, regardless  
of the levels of the enable inputs.  
NC – No internal connection  
The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input  
sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear  
function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets  
all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This  
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum  
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear  
the counter to 0000 (LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this  
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...27

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