SN54LS256

更新时间： 2024-09-29 23:03:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		锁存器双倍数据速率
页数	文件大小	规格书
6页	228K
描述
DUAL 4-BIT ADDRESSABLE LATCH

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中文翻译

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数据手册

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SN54LS256 数据手册

SN54/74LS256

DUAL 4-BIT

ADDRESSABLE LATCH

The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control

inputs;theseincludetwoAddressinputs(A , A ),anactiveLOWEnableinput

DUAL 4-BIT

ADDRESSABLE LATCH

(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and

four outputs (Q –Q ).

When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs

(Q –Q ) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and

E are both LOW. When CL is HIGH and E is LOW, the selected output

(Q –Q ), determined by the Address inputs, follows D. When the E goes

HIGH, the contents of the latch are stored. When operating in the addressable

latch mode (E=LOW, CL=HIGH), changing more than one bit of the Address

LOW POWER SCHOTTKY

(A , A ) could impose a transient wrong address. Therefore, this should be

done only while in the memory mode (E=CL=HIGH).

J SUFFIX

CERAMIC

CASE 620-09

• Serial-to-Parallel Capability

• Output From Each Storage Bit Available

• Random (Addressable) Data Entry

• Easily Expandable

• Active Low Common Clear

• Input Clamp Diodes Limit High Speed Termination Effects

N SUFFIX

PLASTIC

CASE 648-08

CONNECTION DIAGRAM DIP (TOP VIEW)

D SUFFIX

SOIC

CASE 751B-03

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

PIN NAMES

LOADING (Note a)

LOGIC SYMBOL

HIGH

LOW

A , A

Address Inputs

Data Inputs

Enable Input (Active LOW)

Clear Input (Active LOW)

0.5 U.L.

1.0 U.L.

0.5 U.L.

0.25 U.L.

0.5 U.L.

D , D

0.25 U.L.

–Q

Parallel Latch Outputs (Note b)

10 U.L.

5 (2.5) U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) Temperature Ranges.

FAST AND LS TTL DATA

5-421

12 3 4 5 6

中文翻译

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与SN54LS256相关器件

型号	品牌	获取价格	描述	数据表
SN54LS256J	MOTOROLA	获取价格	DUAL 4-BIT ADDRESSABLE LATCH
SN54LS256JD	MOTOROLA	获取价格	LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16
SN54LS256W	MOTOROLA	获取价格	D Latch, 2-Func, 4-Bit, TTL, CDFP16
SN54LS257	MOTOROLA	获取价格	QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS
SN54LS257	TI	获取价格	QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SN54LS257AJ	MOTOROLA	获取价格	Multiplexer, LS Series, 4-Func, 2 Line Input, 1 Line Output, True Output, TTL, CDIP16, CER
SN54LS257AJD	MOTOROLA	获取价格	Multiplexer, LS Series, 4-Func, 2 Line Input, 1 Line Output, True Output, TTL, CDIP16, CER
SN54LS257AW	MOTOROLA	获取价格	IC,LOGIC MUX,QUAD,2-INPUT,LS-TTL,FP,16PIN,CERAMIC
SN54LS257AW-00	TI	获取价格	LS SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDFP16
SN54LS257B	MOTOROLA	获取价格	QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS