Datasheet > SM16M72ALDT-7.5

SM16M72ALDT-7.5

更新时间： 2024-02-24 03:48:16

品牌	Logo	应用领域
铁电 - RAMTRON		动态存储器内存集成电路
页数	文件大小	规格书
15页	197K
描述
Synchronous DRAM Module, 16MX72, 4.5ns, CMOS, DIMM-168

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技术参数
数据手册

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SM16M72ALDT-7.5 技术参数

生命周期：	Obsolete	零件包装代码：	DIMM
包装说明：	,	针数：	168
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.84
访问模式：	DUAL BANK PAGE BURST	最长访问时间：	4.5 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-XDMA-N168
内存密度：	1207959552 bit	内存集成电路类型：	SYNCHRONOUS DRAM MODULE
内存宽度：	72	功能数量：	1
端口数量：	1	端子数量：	168
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	16MX72
封装主体材料：	UNSPECIFIED	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	认证状态：	Not Qualified
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子位置：	DUAL	Base Number Matches：	1

SM16M72ALDT-7.5 数据手册

168-pin Low profile ESDRAM DIMMs

32MB, 64MB, 128MB

Preliminary Data Sheet

Pin Descriptions

Symbol

CK(0:3)

Type

Input

Function

Clocks: All SDRAM input signals are sampled on the positive edge of CK.

CKE(0:1)

Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the

Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until

the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.

S(0:3)#

Input

Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is

disabled, new commands are ignored but previous operations continue.

RAS#, CAS#,

WE#

Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.

Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.

BA(0:1)

A(0:11)

Input

Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-A8 define the column

address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual

Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.

The address inputs are also used to program the Mode Register.

DQ(0:63)

Input/

Output

Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up

and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after

the CAS latency is satisfied.

DQMB(0:7)

CB(0:7)

Input

Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable

(2-cycle latency) for read data.

Input/

Output

Supply

ECC Check Bits

V_DD

V_SS

Power Supply: +3.3 V

Ground

Supply

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into

and data out of the presence-detect portion of the module.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to

and from the module

SA(0:2)

Input

Presence-Detect Address Inputs: These pins are used to configure the presence detect device.

Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low

for normal read/write operations.

RFU

DNU

Reserved for Future Use: These pins should be left unconnected.

Do not use.

No connect - open pin.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

The information contained herein is subject to change without notice.

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Revision 1.0

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