Datasheet > SLG55021-200010V

SLG55021-200010V

更新时间： 2024-01-13 12:08:51

品牌	Logo	应用领域
DIALOG		驱动光电二极管接口集成电路
页数	文件大小	规格书
8页	146K
描述
Controlled Load Discharge Rate

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SLG55021-200010V 技术参数

生命周期：	Transferred	包装说明：	TDFN-8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	3.75
接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER	JESD-30 代码：	S-PDSO-N8
长度：	2 mm	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出电流流向：	SINK
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVSON
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：	0.8 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	温度等级：	MILITARY
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	DUAL	宽度：	2 mm
Base Number Matches：	1

SLG55021-200010V

Application Example

In a typical application, de-asserting ON (low) or asserting the low true Shut Down signal (SHDN#) turns off the external power

N-FET. SHDN# is provided as an asynchronous override to the ON signal. When the FET is turned off, the voltage at the load

is discharged through a resistor (typically 200 ohms) internal to the SLG55021 with the discharge current limited to a maximum

of 10mA. When ON is asserted (high), gate voltage is not applied to the gate of the external power N-FET until after T_DELAYthen

the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage V_Sat a slew rate determined by the internal slew

rate control element internal to the SLG55021. Monotonic rise of Vs is maintained even as ID increases dramatically after the

load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum steady state value, the

Open Drain PG (Power Good) signal is asserted. PG may be used as the ON control of a second SLG55021 thereby providing

power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other PG signals to indicate all

switched power rails are in a power good condition.

The devices will not operate if Vcc is below 3.5V.

The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate

for variations in load current as the voltage is applied.

000-0055021-102

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