SK2111AXFT

更新时间： 2024-02-27 11:50:41

品牌	Logo	应用领域
商升特 - SEMTECH		时钟驱动器
页数	文件大小	规格书
6页	399K
描述
1:10 DIFFERENTIAL LVDS CLOCK DRIVER

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SK2111AXFT 数据手册

SK2111

1:10 Differential LVDS Clock Driver

TEST AND MEASUREMENT PRODUCTS

Features

Description

SK2111 is a 1 to 10 data/clock distributor utilizing

LVDS (Low Voltage Differential Signaling) technology

for high speed operation. Data paths are fully differ-

ential from input-to-output for low noise generation

and low pulse width distortion. The design allows

connection of 1 input to all 10 outputs. LVDS I/O

enable high speed data transmission for point-to-point

interconnects. This device can be used as a high

speed differential 1 to 10 signal distribution / fanout

replacing multi-drop bus applications for higher speed

links with improved signal quality. It can also be

used for clock distribution up to 800 MHz.

Supply Voltage Range: +3.0V to +3.6V

Part-to-part skew 75 ps (Max.)

Output channel-to-channel skew is 60 ps (Max.)

800 MHz minimum toggle frequency

Differential output voltage (DV_OUT) is 350 mV

(typical) with 100 Ω termination load

LVDS receiver inputs accept LVPECL signals

On-chip 100 Ω input termination resistor

Fast propagation delay of 500 ps (typical)

Receiver input threshold <±±11 mV

V_REFfor LVDS single-ended input applications

ESD Protection of >4000V

Industrial Temperature Range: -40^oC to +85^oC

Available in Thermally Enhanced EDQUAD

32 Pin LQFP Package

The SK2111 accepts LVDS signal levels, LVPECL lev-

els directly or PECL with attenuation network resis-

tors. The inputs of SK2111 have an on-chip 100 Ω

termination resistors to minimize the component count.

The OE input is synchronous so that the outputs will

only be enabled/disabled when they are already in the

low state. This feature prevents generating any runt

clocks. The EDQUAD LQFP package has an exposed

heatslug which is connected to VEE substrate.

Conforms to ANSI/TIA/EIA-644 LVDS standard

Pin Description

Functional Block Diagram

24 23 22 21 20 19 18 17

VCC

Q2*

VCC

Q7*

CLK1

Q1*

Q0:Q9

100Ω

Q8*

SK2111

CLK1*

Q0*:Q9*

Q0*

Q9*

VCC

LEN

VCC

REF

1.2V

Pin Names

CLK1, CLK1*

Q0, Q9, Q0*, Q9*

V_REF

Function

Differential LVDS Input Pair

Differential LVDS Outputs

Q0-Q9

LOW

Q0*-Q9*

HIGH

Qn*

LVDS Reference Voltage 1.2V

Output Enable Input LVTTL / LVCMOS

Truth Table

www.semtech.com

Revision 3 / April 24, 2003

12 3 4 5 6

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