Datasheet > SI3216MPPQX-EVB

SI3216MPPQX-EVB

更新时间： 2022-02-26 10:47:20

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
41页	922K
描述
EVALUATION BOARD FOR THE Si3210/15/16 PROSLIC

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SI3216MPPQX-EVB 数据手册

Si321xPPQx-EVB

1.3. ProSLIC Evaluation Board Setup

Table 2. Motherboard Power Connections

J2, J3, J4

To prepare the ProSLIC evaluation board for use,

perform the following steps:

Si321x

Si321xM

1. Set power supplies to 3.3 V, 5 V, and 12 V.

2. With these supplies off, connect them to J3 and J4

corresponding to the silk screen designators.

VBRING

VBHI

VBLO

GND

3. Connect the PC’s parallel port (LPT1) to P1 (or J1)

using a 25-pin D male-to-male cable.

4. Select the on-board PCM clock source, or select an

external PCM source, and connect an Audio

Precision SIA-2322 to P2 and P3 or a Wandel and

Goltermann PCM-4 to J8, J9, J10, and J11.

GND

5. TIP/RING connection can be made from the RJ-11 to

a phone or telephony test equipment.

+3 V

+3.3 V

+5 V

6. Invoke the ProSLIC LINC software.

+VIN

Notes:

+9 to 12 V

+5 V

7. Turn the power supplies on and press the ProSLIC

evaluation board reset button (S1).

1. All three GND connection points are electrically

connected on the board.

8. Click the “Reinitialize” button in the ProSLIC LINC

software panel

2. +3.3 V is only necessary if that is the desired VDD for

operation. Si321x chooses +3.3 V or +5 V based on

the SP1 of the motherboard (see schematic).

3. This may be changed based on application-specific

circuits. Consult the dc-dc converter spreadsheet for

other possible values.

The ProSLIC is now ready to perform its linecard

function.

Table 3. On-Board PCLK Settings (S2)

S2-1,2,3

S2-4

Unused

S2-5

Unused

S2-6

Unused

S2-7

S2-8

PCLK frequency

Unused

FS enable

0,0,0 = 8.192 MHz

0,0,1 = 4.096 MHz

0,1,0 = 2.048 MHz

0,1,1 = 1.024 MHz

1,x,x = 512 kHz

0 = FS disabled

1 = FS enabled

Note: 1 = on.

Table 4. JP1–4 Settings

1–2

Jumper Location

Default Factory

Setting

Jumper

Function

2–3

+5 V

VDD Level Select

VPCM Level Select

FSYNC Level Select

PCLK Source Select

JP1

JP2

JP3

JP4

+3 V

1–2

2–3

1–2

+5 V

Internal

External

Rev. 1.2

1 234 5 6 7...41

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