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SAL-TC397XE-256F300SBC PDF预览

SAL-TC397XE-256F300SBC

更新时间: 2024-09-29 21:11:59
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟微控制器外围集成电路
页数 文件大小 规格书
1页 309K
描述
Microcontroller, 32-Bit, FLASH, 300MHz, CMOS, PBGA292, BGA-292

SAL-TC397XE-256F300SBC 技术参数

是否Rohs认证: 符合生命周期:Not Recommended
包装说明:LFBGA,Reach Compliance Code:compliant
风险等级:5.76具有ADC:YES
地址总线宽度:位大小:32
最大时钟频率:160 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-PBGA-B292长度:17 mm
端子数量:292片上程序ROM宽度:8
最高工作温度:150 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
ROM可编程性:FLASH筛选级别:ISO 26262
座面最大高度:1.7 mm速度:300 MHz
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:17 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

SAL-TC397XE-256F300SBC 数据手册

  
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32-bit Microcontroller (MCU)  
32-bit AURIXMicrocontroller based on TriCore™  
32-bit TriCoreAURIX– TC3xx  
AURIXTC39x Emulation devices  
SAL-TC397XE-256F300S BC  
SAL-TC397XE-256F300S BC  
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Trace, Measurement and Calibration in the target system  
The SAL-TC397XE-256F300S BC belongs to the TC39x Emulation Devices. It has the same feature set as  
the TC39x standard family with additional debug and tracing capabilities. The TC39xXE offers support  
for calibration, rapid prototyping, instrumentation and debug/emulation.  
make  
01_00 | Dec 12, 2018 |  
PDF 10.73 mb  
cars clean, safe  
and smart.  
|
TC39xXE is based on TC39x. It can be used to emulate:  
Product Brochure New  
TriCoreFamily  
TC39x standard devices (6 CPUs)  
TC38x standard devices (4 CPUs)  
01_00  
|
Aug 07, 2019 |  
PDF  
|
11.16 mb  
Microcontroller Pocket  
Guide  
Standards Features  
:
Emulation Features :  
01_01  
|
Aug 21, 2019 |  
PDF  
|
5.14 mb  
TC39xXE has the same features as the TC39x  
4 MB Extension Memory (EMEM) for  
standard devices:  
calibration and tracing (2 MB)  
Multi-Core Debug Solution (MCDS)  
6
TriCore running at 300 MHz  
16 MB flash/ ECC protection  
Parallel and time aligned trace of  
cores and busses  
6,9 MB SRAM/ ECC protection (additional 4 MB  
EMEM)  
Powerful trigger conditions  
1
Gbit Ethernet, 12xCAN FD  
,
2xFlexRay, 12x  
On-chip logic analyzer functions  
ASCLIN, 4xQSPI 2xI²C 25xSENT,, 6xPSI, 2xHSSL,  
,
,
4xMSC, 1x eMMC/SDIO, GTM, GPT, CCU6  
EVITA Full HSM (ECC256 and SHA2)  
LFBGA-292 package  
Additional DAP interface (DAPE) for  
connecting a second independent  
tool  
Injector for faults and stress (IFS)  
Single voltage supply 5 V or 3.3 V  
Aurora Gigabit Trace (AGBT) support  
CPUs have full access to all  
emulation resources, enabling all  
kind of interfaces (e.g. Ethernet) as  
tool  
Benefits  
:
Higher software/system quality and faster time  
to market with best in class:  
Strong AURIXTC3xx compatibility  
Maintains investment in tools and  
knowledge  
Multi-core debugging and trace  
Trace based measurement  
Rapid prototyping  
Early availability of attractive tooling  
solutions  
Minimizes the risk  
Calibration  
Different tool combinations due to two  
DAP interfaces  
Scalable tooling options from very cost effective  
to highest performance  
Very cost effective trace  
Consistent architecture over the whole  
family for all packages  
MCDS tracing can be evaluated using the free of charge MCDS Trace Viewer tool which comes with the  
DAS installation www.infineon.com/DAS  
Compatibility  
Full compatibility with TC39x standard devices. For TC38x systems the following points need to be  
considered:  
Thermal design and power supply need to support the higher TC39xXE power consumption  
SW needs to be tolerant to the different CHIPID and JTAGID values  
The upper 12 ASCLIN modules (out of 24) of TC38x may not be used  
Diagrams  
Ambient temperature  
Single voltage  
supply or 3.3  
5V/3,3 V EVR,  
8-bit SCR  
range  
5
V
-40...+150°C  
Safe DMA  
AUTOSAR  
4.2 support  
-
O26262 -Dr
ISASIL
IEC61r508–SIL3  
v
channels 128  
TriCore™  
300 MHz  
DSP functionality  
EVI
T
AFu  
l
l
H
SM  
I/O3.3V
C
M
OS  
Packag6e
LFBGAt-292
(EC  
C
2
5
6
a
nd
S
H
A2)  
5V inp tADCt pins  
u
o
n
Additional DAP  
interface  
(DAPE)  
Multi-Core Debug  
Solution (MCDS)  
Aurora Gigabit Trace  
(AGBT) support  
TIMER/PWM  
6x STM  
GTM  
1x GPT12  
1x CCU6  
Communication  
12x CAN FD  
4xQSPI  
I²S emulation  
1x Gbit  
Ethernet  
6xPSI  
2xI²C  
2xFlexRay  
2xHSSL  
25xSENT  
4x MSC  
12xASCLIN  
EBU  
1xeMMC  
Memory  
Analog  
4
MB Extension Memory (EMEM)  
124x ADC channels  
for calibration and tracing (2 MB)  
Up to 16 MB flash  
ECC protection  
Up to 6912 KB RAM  
ECC protection  
Parametrics  
Parametrics  
SAL-TC397XE-256F300S BC  
#
of cores  
/
lockstep cores  
6/4  
A/D Input Lines  
ASIL/SIL support  
CAN Nodes  
124  
ASIL-D/ SIL-3  
12  
Clock Frequency  
DMA Channels  
300.0 MHz  
128  
Yes  
Yes  
2
DSP Functionality  
External Bus Interface  
FlexRayTM  
Floating Point Unit  
Hardware Accelerator  
yes  
no  
I/O Operation Voltages min max  
LIN  
3.3 V 5.0 V  
12.0  
12.0  
yes  
Number of ADC Modules  
On-chip Clock Generation  
On-chip Voltage Regulator  
Oscillator Watchdog  
Program Memory  
Real Time Clock  
SPI  
yes  
yes  
16.0 MByte  
yes  
6.0  
SRAM (incl. Cache)  
Temperature  
6912.0 kByte  
-40°C to 150°C  
Flash  
Type of Memory  
Watchdog Timer  
eMMC  
Yes  
yes  
Documents  
Expand all  
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Application Notes  
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Product Brochure  
Application Brochure  
Product Selection Guide  
Presentations  
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Order  
Sales Product Name  
SAL-TC397XE-256F300S BC  
OPN  
TC397XE256F300SBCLXUMA1  
Product Status  
Package name  
Order online  
active and preferred  
PG-LFBGA-292  
Buy online  
yes  
Completely lead free  
Halogen free  
yes  
RoHS compliant  
Packing Size  
yes  
1000  
Packing Type  
Moisture Level  
Moisture Packing  
TAPE  
3
& REEL  
DRY  
Boards  
5
out of 12 boards  
Image  
Board  
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This basic 3.3V TC397 Application Kit  
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TC375TP mounted directly on the board  
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This AURIX2G TC377TX 3.3V  
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software. The TC377TX device is  
mounted on a socket so that it can be  
easily changed, making it particularily  
suitable for early project development.  
NEW  
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