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SA624

更新时间： 2024-02-12 07:02:31
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
15页 162K
描述
High performance low power FM IF system with high-speed RSSI

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SA624 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknown风险等级：5.83
商用集成电路类型：AUDIO DEMODULATOR解调类型：FM
JESD-30 代码：R-PDIP-T16长度：19.025 mm
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
标称输出电压（调频）：530 mV封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
座面最大高度：4.2 mm信噪比Nom（FM）：73 dB
最大压摆率：4.2 mA最大供电电压 (Vsup)：8 V
最小供电电压 (Vsup)：4.5 V表面贴装：NO
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SA624 数据手册

 浏览型号SA624的Datasheet PDF文件第4页浏览型号SA624的Datasheet PDF文件第5页浏览型号SA624的Datasheet PDF文件第6页浏览型号SA624的Datasheet PDF文件第8页浏览型号SA624的Datasheet PDF文件第9页浏览型号SA624的Datasheet PDF文件第10页 
Philips Semiconductors  
Product specification  
High performance low power FM IF system with  
high-speed RSSI  
SA624  
0.5  
SFG455A3  
to  
22pF  
1nF  
0.1µF  
1.3µH  
NE624 TEST CIRCUIT  
0.1µF  
455kHz  
Q=20  
44.545  
3rd OVERTURE  
XTAL  
5.5µH  
5.6pF  
0.1µF  
10  
SFG455A3  
10pF  
+6V  
16  
15  
14  
13  
12  
11  
9
8
8
1
7
6
5
100nF  
10nF  
6.8µF  
0.1µF  
SA624  
SA602A  
2
0.1µF  
3
4
1
2
3
4
5
6
7
47pF  
22pF  
DATA  
OUT  
0.1µF  
0.21  
to  
0.28µH  
100k  
+6V  
V
C–MSG  
FILTER  
CC  
AUDIO  
OUT  
MUTE  
NE624 IF INPUT (µV) (1500Ω)  
100nF  
RSSI  
100k  
10  
100  
1k  
10k  
AUDIO  
–0  
4V  
3V  
2V  
1V  
RSSI (VOLTS)  
–20  
–40  
–60  
THD + NOISE  
AM (80% MOD)  
NOISE  
–80  
–120  
–100  
–80  
–60  
–40  
–20  
NE602 RF INPUT (dBm) (50Ω)  
SR00444  
Figure 5. Typical Application Cellular Radio (45MHz to 455kHz)  
One of the outputs is available at Pin 9 to drive an external  
quadrature capacitor and L/C quadrature tank.  
CIRCUIT DESCRIPTION  
The SA624 is a very high gain, high frequency device. Correct  
operation is not possible if good RF layout and gain stage practices  
are not used. The SA624 cannot be evaluated independent of  
circuit, components, and board layout. A physical layout which  
correlates to the electrical limits is shown in Figure 3. This  
configuration can be used as the basis for production layout.  
Both of the limiting amplifier stages are DC biased using feedback.  
The buffered output of the final differential amplifier is fed back to the  
input through 42kΩ resistors. As shown in Figure 4, the input  
impedance is established for each stage by tapping one of the  
feedback resistors 1.6kΩ from the input. This requires one  
additional decoupling capacitor from the tap point to ground.  
The SA624 is an IF signal processing system suitable for IF  
frequencies as high as 21.4MHz. The device consists of two limiting  
amplifiers, quadrature detector, direct audio output, muted audio  
output, and signal strength indicator (with output characteristic). The  
sub-systems are shown in Figure 4. A typical application with  
45MHz input and 455kHz IF is shown in Figure 5.  
42k  
V+  
15  
16  
700  
14  
7k  
1.6k  
1
40k  
IF Amplifiers  
The IF amplifier section consists of two log-limiting stages. The first  
consists of two differential amplifiers with 39dB of gain and a small  
signal bandwidth of 41MHz (when driven from a 50Ω source). The  
output of the first limiter is a low impedance emitter follower with  
1kΩ of equivalent series resistance. The second limiting stage  
consists of three differential amplifiers with a gain of 62dB and a  
small signal AC bandwidth of 28MHz. The outputs of the final  
differential stage are buffered to the internal quadrature detector.  
SR00445  
Figure 6. First Limiter Bias  
Because of the very high gain, bandwidth and input impedance of  
the limiters, there is a very real potential for instability at IF  
frequencies above 455kHz. The basic phenomenon is shown in  
Figure 8. Distributed feedback (capacitance, inductance and  
radiated fields)  
7
1997 Nov 07  
1...45678910...15

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