NMOS linear image sensor S3921/S3924 series
ꢀ
Shape specifications
Parameter
S3921-
128Q
128
S3921-
256Q
256
S3921-
512Q
512
S3924-
256Q
256
S3924-
512Q
512
S3924-
1024Q
1024
Unit
Number of pixels
Package length
Number of pin
-
mm
31.75
40.6
31.75
40.6
22
Quartz
22
Quartz
-
-
Window material *3
Weight
*3: Fiber optic plate is available.
3.0
3.5
3.0
3.5
g
ꢀ Specifications (Ta=25 °C)
S3921 series
Typ.
S3924 series
Typ.
25
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
pitc Pixel
h
-
-
-
-
50
2.5
-
-
-
-
-
-
µ
m
Pixel height
2.5
mm
nm
nm
pA
pF
Spectral response range (10 % of peak)
Peak sensitivity wavelength
Photodiode dark current *4
λ
λp
200 to 1000
600
0.2
200 to 1000
600
0.1
-
-
-
-
-
-
-
-
-
-
0.6
-
-
-
-
-
-
-
-
-
-
0.3
ID
Photodiode capacitance *4
Cph
Esat
Qsat
20
220
-
-
10
220
-
-
5
Saturation exposure *4,
Saturation charge *4
*
m
lx · s
pC
50
-
25
-
1350 (-128Q)
1300 (-256Q)
1100 (-512Q)
-
-
1050 (-256Q)
820 (-512Q)
570 (-1024Q)
-
-
mV
mV
mV
%
Saturation output voltage *4
Vsat
-
-
-
±3
-
±3
Photo response non-uniformity *6
PRNU
*4: Reset V=2.5 V, Vdd=5.0 V, V
*5: 2856 K, tungsten lamp
*6: 50 % of saturation, excluding the start pixel and last pixel
φ
=5.0 V
ꢀ
Electrical characteristics (Ta=25 °C)
Parameter Symbol
1, V 2 (H)
S3921 series
Typ.
S3924 series
Typ.
Condition
Unit
Min.
4.5
0
Max.
Min.
4.5
0
Max.
10
V
φ
φ
High
Low
High
Low
High
Low
-
-
-
-
-
-
-
-
-
-
5
-
10
0.4
10
5
-
V
V
V
V
V
V
V
V
V
V
Clock pulse ( 1, 2)
φ φ
voltage
V
φ
V
1, V 2 (L)
s (H)
s (L)
φ
0.4
10
φ
φ
V
φ
φ
φ
V
φ
φ
φ
4.5
0
4.5
0
Start pulse (
φ
st) voltage *7
V
-
0.4
10
-
0.4
10
Vr
φ
φ
(H)
(L)
V
V
4.5
0
4.5
0
Reset pulse (Reset
voltage *7
Source follower circuit drain voltage *7
φ
)
Vr
-
0.4
10
-
0.4
10
Vdd
4.5
2.0
-
4.5
2.0
-
V
V
Reset voltage (Reset V) *8
Vr
Vscg
Vscd
V
φ
- 2.5
0
Vr
V
φ
- 2.0
V
φ
- 2.5
0
Vr
φ
V - 2.0
Saturation control gate voltage
Saturation control drain voltage *8
-
-
-
-
-
-
tr 1, tr 2
φ
φ
Clock pulse (
φ
1,
φ
2) rise / fall time
-
-
20
-
-
20
-
ns
tfφ1, tfφ2
Clock pulse (
φ
1, φ2) pulse width
st) rise / fall time
-
-
-
-
200
-
-
-
-
-
200
-
-
-
-
-
ns
ns
ns
ns
tpwφ1, tpwφ2
Start pulse (
φ
-
200
-
20
-
-
200
-
20
-
tr s, tf s
φ
φ
Start pulse (
φ
st) pulse width
tpwφs
Reset pulse rise / fall time
Start pulse ( st) and clock pulse
2) overlap
Clock pulse (
20
20
trr , tfr
φ
φ
φ
-
-
-
200
660
50
-
-
-
-
-
-
200
660
50
-
-
-
-
-
-
ns
ns
ns
t ov
φ
(
φ
φ
2) and reset
tφovr
pulse (Reset
Clock pulse (
pulse (Reset
Clock pulse (
Clock pulse (
Data rate *10
φ
) overlap
φ
2) and reset
) delay time
1,
2) space *9
2, Reset
) space *9
tdφr-2
φ
φ
φ
φ
X1, X2
tsφr-2
f
-
-
-
trf - 20
-
-
-
-
trf - 20
-
-
-
-
-
ns
ns
φ
0
-
0
0.1
500
0.1
500
kHz
ns
-
-
-
-
-
-
100 (-128 Q)
150 (-256 Q)
200 (-512 Q)
21 (-128 Q)
36 (-256 Q)
67 (-512 Q)
-
-
-
-
-
-
-
-
-
-
-
-
100 (-256 Q)
150 (-512 Q)
200 (-1024 Q)
27 (-256 Q)
-
-
-
-
-
-
50 % of
saturation *10
Video delay time
tvd
ns
ns
pF
pF
pF
Clock pulse (
φ1, φ2)
5 V bias
5 V bias
5 V bias
50 (-512 Q)
100 (-1024 Q)
Cφ
Cr
line capacitance
Reset pulse (Reset
line capacitance
φ
)
-
6
-
-
6
-
pF
-
-
-
12 (-128 Q)
20 (-256 Q)
35 (-512 Q)
-
-
-
-
-
-
14 (-256 Q)
24 (-512 Q)
45 (-1024 Q)
-
-
-
pF
pF
pF
Saturation control gate (Vscg)
line capacitance
Cscg
Zo
Vdd=5 V
Vr=2.5 V
Output impedance
-
200
-
-
200
-
Ω
φ
*7: V is input pulse voltage (refer to figure 8)
*8: Terminal pin 7 is used for both Reset V and saturation control drain voltage
*9: trf is the clock pulse rise or fall time. A clock pulse space of rise time/fall time - 20 ns (nanoseconds) or more
should be input if the clock pulse rise or fall time is longer than 20 ns. (refer to figure 7)
φ
*10: Reset V=2.5 V, Vdd=5.0 V, V =5.0 V
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