NMOS linear image sensor S3902/S3903 series
ꢀ Shape specifications
S3902-
128Q
128
S3902-
256Q
256
S3902-
512Q
512
S3903-
256Q
256
S3903-
512Q
512
S3903-
1024Q
1024
Parameter
Unit
Number of pixels
Package length
Number of pin
-
mm
31.75
40.6
31.75
40.6
22
Quartz
22
Quartz
-
-
Window material *3
Weight
*3: Fiber optic plate is available.
3.0
3.5
3.0
3.5
g
ꢀ Specifications (Ta=25 °C)
S3902 series
S3903 series
Parameter
Symbol
Unit
Min.
Typ.
50
Max.
Min.
Typ.
25
Max.
pitcPixel
h
-
-
-
-
-
-
-
-
-
-
µm
mm
Pixel height
Spectral response range
(10 % of peak)
0.5
0.5
200 to 1000
200 to 1000
nm
λ
Peak sensitivity wavelength
Photodiode dark current *4
-
-
-
-
-
-
600
0.08
4
-
-
-
-
-
-
-
600
0.04
2
-
nm
pA
λp
ID
0.15
0.08
Photodiode capacitance *4
Cph
Esat
Qsat
PRNU
-
-
-
-
pF
mlx · s
pC
5
Saturation exposure *4,
*
180
10
180
5
Saturation output charge *4
-
±3
-
±3
Photo response non-uniformity *6
-
-
%
*4: Vb=2.0 V, Vφ=5.0 V
*5:
2856 K, tungsten lamp
*6:
50 % of saturation, excluding the start pixel and last pixel
ꢀ Electrical characteristics (Ta=25 °C)
S3902 series
Typ.
S3903 series
Typ.
Parameter
Symbol
Condition
Unit
Min.
4.5
0
Max.
Min.
Max.
10
High
Low
High
Low
-
-
-
-
-
-
-
5
10
0.4
10
4.5
0
5
V
V
V
V
V
V
V
Vφ1, Vφ2 (H)
Vφ1, Vφ2 (L)
Vφs (H)
Vφs (L)
Clock pulse (φ1, φ2)
voltage
-
Vφ1
-
-
Vφ1
-
0.4
10
4.5
0
4.5
0
Start pulse (φst) voltage
Video bias voltage *7
0.4
0.4
Vb
1.5
-
1.5
-
Vφ - 3.0 Vφ - 2.5
Vφ - 3.0 Vφ - 2.5
Saturation control gate voltage
Saturation control drain voltage
Vscg
Vscd
0
Vb
-
0
Vb
-
-
-
-
-
trφ1, trφ2
tfφ1, tfφ2
tpwφ1, tpwφ2
trφs, tfφs
tpwφs
Clock pulse (
φ
1,
2) rise / fall time *8
φ
-
-
20
-
-
20
-
ns
-
-
-
200
-
-
20
-
-
-
-
200
-
-
20
-
-
-
-
ns
ns
ns
Clock pulse (φ1, φ2) pulse width
Start pulse (φst) rise / fall time
Start pulse (φ1, φ2) pulse width
Start pulse (φst) and clock pulse
(φ2) overlap
200
200
-
200
-
-
200
-
-
ns
tφov
Clock pulse space *8
X1, X2
f
-
-
trf - 20
0.1
-
-
2000
trf - 20
0.1
-
-
2000
ns
kHz
ns
Data rate *9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70 (-128 Q)
110 (-256 Q)
140 (-512 Q)
21 (-128 Q)
36 (-256 Q)
67 (-512 Q)
12 (-128 Q)
20 (-256 Q)
35 (-512 Q)
7 (-128 Q)
11 (-256 Q)
20 (-512 Q)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80 (-256 Q)
120 (-512 Q)
160 (-1024 Q)
27 (-256 Q)
50 (-512 Q)
100 (-1024 Q)
12 (-256 Q)
24 (-512 Q)
45 (-1024 Q)
10 (-256 Q)
16 (-512 Q)
30 (-1024 Q)
-
-
-
-
-
-
-
-
-
-
-
-
50 % of
saturation
*9, *10
Video delay time
tvd
Cφ
ns
ns
pF
pF
pF
pF
pF
pF
pF
pF
pF
Clock pulse (φ1, φ2)
line capacitance
5 V bias
5 V bias
2 V bias
Saturation control gate (Vscg)
line capacitance
Cscg
CV
Video line capacitance
*7: Vφ is input pulse voltage (refer to figure 8)
*8: trf is the clock pulse rise or fall time. A clock pulse space of rise time/fall time - 20 ns (nanoseconds) or more should be
input if the clock pulse rise or fall time is longer than 20 ns. (refer to figure 7)
*9: Vb=2.0 V, Vφ=5.0 V
*10: Measured with C7883 driver circuit.
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