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S29WS128PABBFW200 PDF预览

S29WS128PABBFW200

更新时间： 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
91页 996K
描述
Flash, 8MX16, 80ns, PBGA84, FBGA-84

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S29WS128PABBFW200 数据手册

 浏览型号S29WS128PABBFW200的Datasheet PDF文件第85页浏览型号S29WS128PABBFW200的Datasheet PDF文件第86页浏览型号S29WS128PABBFW200的Datasheet PDF文件第87页浏览型号S29WS128PABBFW200的Datasheet PDF文件第88页浏览型号S29WS128PABBFW200的Datasheet PDF文件第89页浏览型号S29WS128PABBFW200的Datasheet PDF文件第91页 
S29WS512P  
S29WS256P  
S29WS128P  
SUPPLEMENT  
13. Revision History  
Document Title:S29WS512P, S29WS256P, S29WS128P  
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V, Simultaneous Read/Write Flash  
Document Number: 002-01747  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
Spansion Publication Number: S30MS02GR_SP1_QDB  
A6:Features: Removed Zero Hold mode  
Switching Waveforms: Revised VCC Power-up diagram  
11/03/2006  
11/08/2006  
03/09/2007  
Timing Diagrams: Changed tCR to tRDY in figure 11.7 and figure 11.8  
A7:Features: Updated Effective Write Buffer Programming Per Word  
Erase/Program Timing: tESL changed to Max  
tPSL changed to Max  
CMOS Compatible: Removed Note 2 from table.  
A8:Asynchronous Mode Read: Changed tCR to tRDY in figures 11.9 through 11.12  
Common Flash Memory Interface: Revised Device Geometry table:  
Changed WS512P data to 00FDh  
Address 32h - Data changed to 001h  
Address 33h - Data changed to 000h  
Address 34h - Data changed to 002h  
Revised CFI table: removed Uniform Bottom, Uniform Top, and All sectors for Address  
4Fh  
DC Characteristics: Revised ICCB Burst table  
A9:DC Characteristics: Revised ICCB for 108 MHz frequencies to TBA  
Synchronous/Burst Read: Revised tRACC to 7.6 ns  
Asynchronous Mode Read: Revised tAAVDH to 4 ns  
03/27/2007  
04/20/2007  
A10:AC Characteristics:  
Removed wait state below 14 MHz, wait state 2  
Added additional wait state to all wait state frequency in table 11.4  
Added Continuous Burst Mode Synchronous Wait State Requirement table  
Revised Burst Access Time to (WS-1) * tCK + (tBACC)  
**  
-
WIOB  
A11:Data Sheet Status: Changed to Production  
09/28/2007  
Global: Changed all 108 MHz to 104 MHz  
Latency: Added 10 wait state and 11 wait state latency tables  
Configuration Registers: Added two more configurations to CR0.11 for 10th and 11th  
rising CLK edge  
AC Characteristics: Revised tCES to 6 ns  
Revised tAVD to tCLK  
DC Characteristics: Changed description of ICC2 to VCC Active Program/Erase Cur-  
rent  
Change descritpion of ICC5 to VCC Active Current (Read while Program/Erase)  
Erase/Program Timing and Performance:  
Revised:  
tERS to 40 µs  
tESL to 40 µs  
tPSL to 40 µs  
tPRS to 40 µs  
Output Slew Rate:  
Deleted Programmable Outuput Slew Rate Control section  
A12:Configuration Registers: Changed CR0.14 default setting to 1  
AC Characteristics: Added device Vcc ramp rate limit. Updated timing diagrams for  
Synchronous/Burst Read, Asynchronous Program Operation, Synchronous Program  
Operation, and Chip Sector Erase Command Sequence.  
01/28/2008  
Program/Erase Operations: Added details to Program and Erase Suspend/Resume  
operations  
*A  
*B  
5046533  
5790689  
WIOB  
NIBK  
12/14/2015  
06/29/2017  
Updated to Cypress Template  
Updated to Cypress Logo and Copyright.  
Document Number: 002-01747 Rev. *B  
Page 90 of 91  
1...8788899091

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S29WS128POLBAW003 CYPRESS

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S29WS128POPBFW000 CYPRESS

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S29WS128POPBFW002 CYPRESS

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S29WS128POSBAW002 CYPRESS

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 		Flash, 8MX16, 9ns, PBGA84
S29WS128POSBFW003 CYPRESS

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 		Flash, 8MX16, 9ns, PBGA84,
S29WS128R0PBHW000 CYPRESS

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 		Flash, 32MX16, 80ns, PBGA84, 11.60 X 8 MM, HALOGEN FREE AND LEAD FREE, FBGA-84
S29WS128R0PBHW003 SPANSION

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 		Flash, 32MX16, 80ns, PBGA84, 11.60 X 8 MM, HALOGEN FREE AND LEAD FREE, FBGA-84
S29WS128R0PBHW200 SPANSION

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 		Flash, 32MX16, 80ns, PBGA84, 11.60 X 8 MM, HALOGEN FREE AND LEAD FREE, FBGA-84
S29WS128R0PBHW202 SPANSION

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 		Flash, 32MX16, 80ns, PBGA84, 11.60 X 8 MM, HALOGEN FREE AND LEAD FREE, FBGA-84

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