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QL16X24B-0CG68M PDF预览

QL16X24B-0CG68M

更新时间: 2024-01-28 10:04:08
品牌 Logo 应用领域
其他 - ETC 军事
页数 文件大小 规格书
16页 334K
描述
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

QL16X24B-0CG68M 数据手册

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Military 5.0V pASIC 1 Family  
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA  
Military 5.0V pASIC 1 Family  
D
EVICE  
H
IGHLIGHTS  
FEATURES  
Device Highlights  
Features  
Total of 180 I/O pins  
Very High Speed  
-172 Bidirectional Input/Output pins  
-6 Dedicated Input/High-Drive pins  
ViaLink“ metal-to-metal programmable technol-  
ogy, allows counter speeds over 150 MHz and  
logic cell delays of under 2 ns at 5V, and over 80  
MHz at 3.3V operation.  
-2 Clock/Dedicated input pins with fanout-  
independent, low-skew clock networks  
-PCI 2.1 Compliant I/Os  
High Usable Density  
Input + logic cell + output delays under 6 ns  
Chip-to-chip operating frequencies up to 110 MHz  
Internal state machine frequencies up to 150 MHz  
Clock skew < 0.5 ns  
Up to a 24-by-32 array of 768 logic cells provides  
22,000 usable PLD gates in 208-pin PQFP and  
208-pin CQFP packages.  
PCI-Output Drive  
Input hysteresis provides high noise immunity  
Fully PCI 2.1 compliant input/output capability.  
(including drive current)  
Built-in scan path permits 100% factory testing of  
logic and I/O cells and functional testing with Auto-  
matic Test Vector Generation (ATVG) software  
after programming  
208 pin PQFP pin for pin compatible with the  
208 CQFP  
0.65µ CMOS process with ViaLink programming  
technology  
ASIC  
Gates  
PLD  
Gates  
Max  
I/O  
Qualification  
Level  
SMD  
5962-  
Device  
Package  
QL8x12B  
1,000  
2,000  
4,000  
7,000  
68CPGA  
84CPGA  
64  
76  
M
QL12x16B 2,000  
QL16x24B 4,000  
M, /883  
M, /883  
M, /883  
M, /883  
M
96836  
95599  
95599  
96837  
144CPGA 122  
160 CQFP 122  
QL24x32B 8,000 14,000 208CQFP 180  
208PQFP 180  
M = Military Temperature (-55 to +125 degrees C)  
/883 = MIL-STD-883 qualified  
TABLE 1: Selector Table  
Rev B  
8-7  

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