Datasheet > QG80333M800,SL8CE

QG80333M800,SL8CE

更新时间： 2024-02-28 19:45:01

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
75页	1233K
描述
Micro Peripheral IC, PBGA829,

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技术参数
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QG80333M800,SL8CE 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA829,29X29,50	Reach Compliance Code：	compliant
风险等级：	5.65	JESD-30 代码：	S-PBGA-B829
端子数量：	829	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA829,29X29,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	1.35,1.5,1.8/2.5,3.3 V	认证状态：	Not Qualified
子类别：	Other Microprocessor ICs	表面贴装：	YES
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	Base Number Matches：	1

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Intel^®80333 I/O Processor

Datasheet

Product Features

■ Integrated Intel XScale^®core

—500, 667 and 800 MHz

■ Dual-Ported Memory Controller

—PC2700 Double Data Rate (DDR333)

SDRAM

—ARM* V5TE Compliant

—DDRII 400 SDRAM

—32 KByte, 32-way Set Associative

Instruction Cache with cache locking

—Up to 2 GB of 64-bit DDR333

—Up to 1 GB of 64-bit DDRII400

—32 KByte, 32-way Set Associative Data

Cache with cache locking. Supports

write through or write back

—Optional Single-bit Error Correction,

Multi-bit Detection Support (ECC)

—2 KByte, 2-way Set Associative Mini-

Data Cache

—Supports Unbuffered or Registered

DIMMs and Discrete SDRAM

—128-Entry Branch Target Buffer

—8-Entry Write Buffer

—32-bit memory support

■ DMA Controller

—4-Entry Fill and Pend Buffer

—Performance Monitor Unit

■ Internal Bus 333 MHz/64-bit

■ PCI Express*-to-PCI Bridges

—x8 PCI Express* Upstream Link

—Two Independent Channels Connected

to Internal Bus

—Two 1KB Queues in Ch0 and Ch1

—CRC-32C Calculation

■ Application Accelerator Unit

—RAID6 support

—PCI Express* Specification 1.0a

compliant

—Performs optional XOR on Read Data

—PCI-X Bus A (IOP bus - ATU interface)

—Compute Parity Across Local Memory

Blocks

—PCI-X Bus B (Slot Expansion bus)

supports standard PCI Hot-Plug

Controller

—1 KB/512 byte Store Queue

■ Two UART (16550) Units

—64-byte Receive and Transmit FIFOs

—4-pin, Master/Slave Capable

■ Peripheral Bus Interface

—Four output clocks per PCI-X bus

■ Address Translation Unit

—2 KB or 4 KB Outbound Read Queue

—4 KB Outbound Write Queue

—8-/16-bit Data Bus with Two Chip Selects

■ Interrupt Controller Unit

—4 KB Inbound Read and Write Queue

—Connects Internal Bus to PCI/X Bus A

—Messaging Unit and Expansion ROM

—Four Priority Levels

—Vector Generation

■ Two Programmable 32-bit Timers and

—Sixteen External Interrupt Pins with

High Priority Interrupt (HPI#)

Watchdog Timer

■ Eight General Purpose I/O Pins

■ Two I²C Bus Interface Units

■ 829-Ball, Flip Chip Ball Grid Array (FCBGA)

—37.5 mm²and 1.27 mm ball pitch

Order Number: 305433, Revision: 003US

July 2005

12 3 4 5 6 7...75

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