PSD4XX Family
PSD4XX/ZPSD4XX
Field-Programmable Microcontroller Peripherals
Table of Contents
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9
Introduction...........................................................................................................................................................1
Key Features ........................................................................................................................................................2
Notation ................................................................................................................................................................3
Zero-Power Background.......................................................................................................................................3
Integrated Power ManagementTM Operation........................................................................................................5
Design Flow..........................................................................................................................................................6
PSD4XX Family....................................................................................................................................................7
Table 2. PSD4XX Pin Descriptions......................................................................................................................8
The PSD4XX Architecture ..................................................................................................................................10
9.1 The ZPLD Block..........................................................................................................................................10
9.1.1 The PSD4XXA1 ZPLD Block............................................................................................................10
9.1.1.1 The DPLD ..........................................................................................................................12
9.1.1.2 The GPLD ..........................................................................................................................13
9.1.1.3 TPA Macrocell Structure ...................................................................................................13
9.1.1.4 Port B Macrocell Structure .................................................................................................17
9.1.1.5 The ZPLD Power Management..........................................................................................18
9.1.2 The PSD4XXA2 ZPLD Block............................................................................................................22
9.1.2.1 The DPLD ..........................................................................................................................24
9.1.2.2 The GPLD ..........................................................................................................................26
9.1.2.3 Port A Macrocell Structure .................................................................................................26
9.1.2.4 Port B Macrocell Structure .................................................................................................30
9.1.2.5 Port E Macrocell Structure .................................................................................................33
9.1.2.6 The ZPLD Power Management..........................................................................................34
9.2 Bus Interface...............................................................................................................................................37
9.2.1 Bus Interface Configuration..............................................................................................................37
9.2.2 PSD4XX Interface to a Multiplexed Bus...........................................................................................38
9.2.3 PSD4XX Interface to Non-Multiplexed Bus ......................................................................................38
9.2.4 Data Byte Enable..............................................................................................................................42
9.2.5 Optional Features.............................................................................................................................43
9.2.6 Bus Interface Examples....................................................................................................................43
9.3 I/O Ports......................................................................................................................................................48
9.3.1 Standard MCU I/O............................................................................................................................48
9.3.2 PLD I/O ...........................................................................................................................................48
9.3.3 Address Out......................................................................................................................................49
9.3.4 Address In ........................................................................................................................................49
9.3.5 Data Port ..........................................................................................................................................49
9.3.6 Alternate Function In ........................................................................................................................49
9.3.7 Peripheral I/O ...................................................................................................................................50
9.3.8 Open Drain Outputs..........................................................................................................................50
9.3.9 Port Registers...................................................................................................................................51
9.3.10 Port A – Functionality and Structure.................................................................................................54
9.3.11 Port B – Functionality and Structure.................................................................................................54
9.3.12 Port C and Port D – Functionality and Structure ..............................................................................57
9.3.13 Port E – Functionality and Structure.................................................................................................57
9.4 Memory Block .............................................................................................................................................61
9.4.1 EPROM ............................................................................................................................................61
9.4.2 SRAM ...............................................................................................................................................61
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