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PL663-19 PDF预览

PL663-19

更新时间: 2024-02-09 09:11:48
品牌 Logo 应用领域
PLL 倍频器
页数 文件大小 规格书
15页 484K
描述
Analog Frequency Multiplier

PL663-19 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.37安装特点:SURFACE MOUNT
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装等效代码:LCC16,.12SQ,20电源:2.5/3.3 V
子类别:RF/Microwave Frequency Multipliers最大压摆率:75 mA
表面贴装:YES技术:CMOS

PL663-19 数据手册

 浏览型号PL663-19的Datasheet PDF文件第6页浏览型号PL663-19的Datasheet PDF文件第7页浏览型号PL663-19的Datasheet PDF文件第8页浏览型号PL663-19的Datasheet PDF文件第10页浏览型号PL663-19的Datasheet PDF文件第11页浏览型号PL663-19的Datasheet PDF文件第12页 
Analog Frequency Multiplier  
PL660 and PL663 XO Families  
ELECTRICAL SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS  
PARAMETERS  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage  
VDD  
VI  
4.6  
VDD+0.5  
VDD+0.5  
+150  
+85  
V
Input Voltage, DC  
GND-0.5  
GND-0.5  
-55  
V
Output Voltage, DC  
VO  
V
Storage Temperature  
TS  
°C  
°C  
°C  
°C  
°C  
Industrial Ambient Operating Temperature  
Commercial Ambient Operating Temperature  
Junction Temperature  
TA_I  
TA_C  
TJ  
-40  
0
+70  
125  
Lead Temperature (soldering, 10s)  
260  
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the  
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other  
conditions above the operational limits noted in this specification is not implied.  
PECL ELECTRICAL CHARACTERISTICS  
PARAMETERS  
SYMBOL CONDITIONS  
MIN.  
TYP.  
MAX. UNITS  
Supply Current (with loaded outputs)  
IDD  
Fout = 212.5 MHz  
@ VDD – 1.3V  
58  
65  
75  
mA  
V
Operating Supply Voltage  
Output Clock Duty Cycle  
Short Circuit Current  
VDD  
2.25  
45  
3.63  
50  
50  
55  
%
mA  
V
RL = 50 Ω to  
VDD – 2V  
Output High Voltage  
VOH  
V
DD – 1.025  
VDD  
1.620  
Output Low Voltage  
Clock Rise Time  
Clock Fall Time  
VOL  
tr  
RL = 50 Ω to VDD – 2V  
@20/80%  
V
0.25  
0.25  
0.45  
0.45  
ns  
ns  
tf  
@80/20%  
PECL Levels Test Circuit  
PECL Transistion Time Waveform  
DUTY CYCLE  
OUT  
VDD  
45 - 55%  
55 - 45%  
50Ω  
2.0V  
OUT  
80%  
50Ω  
20%  
OUT  
OUT  
tR  
tF  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991  
www.phaselink.com  
Rev. 3/20/07 Page 9  

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