Datasheet > PL600-27TSI

PL600-27TSI

更新时间： 2024-01-17 21:04:37

品牌	Logo	应用领域
麦瑞 - MICREL		石英晶振
页数	文件大小	规格书
7页	358K
描述
Low Power 3 Output XO

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数据手册

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PL600-27TSI 数据手册

PL600-27T

Low Power 3 Output XO

FEATURES

PIN ASSIGNMENT



3 LVCMOS outputs with OE tri-state control

Low current consumption:

o <4.5mA @ 27MHz, 3.3V

10 to 52MHz fundamental crystal input

1 to 100MHz reference clock input

Accepts both LVCMOS and sine wave inputs

Low phase noise (-130 dBc @ 10kHz offset)

Low jitter (RMS): 2.5ps period jitter

12mA drive capability at TTL output

1.8V to 3.3V operation

XIN/FIN

OE^

XOUT

CLK0

VDD



CLK1

GND

CLK2

SOP-8L

^: Denotes internal Pull-up

Available in GREEN/RoHS 8-pin SOP and 6-pin

SOT23 packages

DESCRIPTION

CLK1

CLK2

VDD

The PL600-27T is a low cost XO IC, designed to re-

place multiple XO solutions saving the cost and

board space of clock distribution buffers. In addition,

it provides among the lowest current on the market

for the 10MHz to 52MHz range. The PL600-27T ac-

cepts crystal and clock inputs from 10 to 52MHz

(fundamental resonant mode crystal) and provides

low phase noise (<-130dBc at 10kHz offset at

30MHz), and very low jitter (2.5 ps RMS period jitter)

outputs.

GND

FIN

CLK0

SOT23-6L

BLOCK DIAGRAM

CLK0

CLK1

CLK2

XIN/FIN

Xtal

Osc

XOUT

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 6/24/10 Page 1

12 3 4 5 6 7

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