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PIC32MM0128GPM036-I/M2 PDF预览

PIC32MM0128GPM036-I/M2

更新时间： 2023-01-03 00:53:33
品牌 Logo 应用领域
美国微芯 - MICROCHIP 微控制器
页数 文件大小 规格书
356页 3690K
描述
RISC Microcontroller, 32-Bit, FLASH, 25MHz, CMOS, PQCC36

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PIC32MM0128GPM036-I/M2 数据手册

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PIC32MM0256GPM064 FAMILY  
32-Bit Flash Microcontroller with MIPS32® microAptiv™ UC Core,  
Low Power and USB  
Operating Conditions  
Peripheral Features  
•
2.0V to 3.6V, -40ºC to +125ºC, DC to 25 MHz  
•
USB 2.0 Compliant Full-Speed and Low-Speed Device,  
Host and On-The-Go (OTG) Controller:  
Low-Power Modes  
-
-
Dedicated DMA  
Device mode operation from FRC oscillator;  
no crystal oscillator required  
•
Low-Power modes:  
-
-
Idle – CPU off, peripherals run from system clock  
Sleep – CPU and peripherals off:  
•
Atomic Set, Clear and Invert Operation on Select  
Peripheral Registers  
High-Current Sink/Source  
Independent, Low-Power 32 kHz Timer Oscillator  
Three 4-Wire SPI modules:  
-
-
-
Three I C Master and Slave w/Address Masking and  
IPMI Support  
Three Enhanced Addressable UARTs:  
-
-
External Edge and Level Change Interrupt on All Ports  
Hardware Real-Time Clock and Calendar (RTCC)  
Up to 24 Peripheral Pin Select (PPS) Remappable Pins  
21 Total 16-Bit Timers:  
-
-
-
- Fast wake-up Sleep with retention  
- Low-power Sleep with retention  
•
•
•
•
0.65 μA Sleep current for RAM Retention   
Regulator mode and 5 μA for Regulator Standby mode  
On-Chip 1.8V Voltage Regulator (VREG)  
16-byte FIFO  
Variable width  
•
•
On-Chip Ultra Low-Power Retention Regulator  
2
I S mode  
2
•
•
High-Performance 32-Bit RISC CPU  
•
•
microAptiv™ UC 32-Bit Core with 5-Stage Pipeline  
microMIPS™ Instruction Set for 35% Smaller Code and  
98% Performance compared to MIPS32 Instructions  
1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance  
RS-232, RS-485 and LIN/J2602 support  
®
IrDA with on-chip hardware encoder and decoder  
•
•
•
•
•
•
•
•
®
3.17 CoreMark /MHz (79 CoreMark) Performance  
16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path  
Two Sets of 32 Core Register Files (32-bit) to Reduce  
Interrupt Latency  
Three dedicated 16-bit timers/counters  
Two can be concatenated to form a 32-bit timer  
Two additional 16-bit timers in each MCCP and  
SCCP module, totaling 18  
•
•
Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply  
64-Bit, Zero Wait State Flash with ECC to Maximize  
Endurance/Retention  
•
Capture/Compare/PWM/Timer modules:  
Microcontroller Features  
-
-
-
Two 16-bit timers or one 32-bit timer in each module  
PWM resolution down to 21 ns  
Three Multiple Output (MCCP) modules:  
•
Up to 256K Flash Memory:  
-
-
-
20,000 erase/write cycle endurance  
20 years minimum data retention  
-
Flexible configuration as PWM, input capture,  
output compare or timers  
Self-programmable under software control  
- Six PWM outputs  
•
•
Up to 32K SRAM Memory  
-
-
Programmable dead time  
Auto-shutdown  
Multiple Interrupt Vectors with Individually   
Programmable Priority  
-
Six Single Output (SCCP) modules:  
•
•
Fail-Safe Clock Monitor mode  
Configurable Watchdog Timer with On-Chip, Low-Power  
RC Oscillator  
-
Flexible configuration as PWM, input capture,  
output compare or timers  
-
Single PWM output  
•
•
Programmable Code Protection  
Selectable Oscillator Options Including:  
•
•
Reference Clock Output (REFO)  
Four Configurable Logic Cells (CLCs) with Internal  
Connections to Select Peripherals and PPS  
Four-Channel Hardware DMA with Automatic Data Size  
Detection and CRC Engine  
-
High-precision, 8 MHz Internal RC (FRC)  
Oscillator – 2x/3x/4x/6x/12x/24x PLL, which can be  
clocked from FRC or the Primary Oscillator  
Primary high-speed, crystal/resonator oscillator or  
external clock  
•
-
Debug Features  
•
Two Programming and Debugging Interfaces:  
-
Two-wire ICSP™ interface with non-intrusive access  
and real-time data exchange with application  
Four-wire MIPS standard Enhanced JTAG interface  
®
-
•
IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan  
2016-2019 Microchip Technology Inc.  
DS60001387D-page 1  
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