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PI74FCT2273TL

更新时间： 2024-09-29 23:27:43
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 239K
描述
Octal D-Type Flip-Flop

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中文翻译

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PI74FCT2273TL 数据手册

 浏览型号PI74FCT2273TL的Datasheet PDF文件第2页浏览型号PI74FCT2273TL的Datasheet PDF文件第3页浏览型号PI74FCT2273TL的Datasheet PDF文件第4页 
PI74FCT273T  
(25Ω Series) PI74FCT2273T  
Fast CMOS Octal D Flip-Flop  
with Master Reset  
Product Description  
Product Features  
• PI74FCT273/2273TispincompatiblewithbipolarFAST™  
Series at a higher speed and lower power consumption  
• 25Ω series resistor on all outputs (FCT2XXX only)  
• TTL input and output levels  
• Low ground bounce outputs  
• Extremely low static power  
• Hysteresis on all inputs  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.6/0.8 micron CMOS  
technology, achieving industry leading speed grades. All  
PI74FCT2XXX devices have a built-in 25-ohm series resistor on  
all outputs to reduce noise because of reflections, thus eliminating  
the need for an external terminating resistor.  
The PI74FCT273T and PI74FCT2273T is an 8-bit wide octal  
designedwitheightedge-triggeredD-typeflip-flopswithindividual  
D inputs and O outputs. The common buffered Clock (CP) and  
Master Reset (MR) load and resets (clear) all flip-flops  
simultaneously. The register is fully edge-triggered. The D input  
state, one setup time before the LOW-to-HIGH clock transition, is  
transferred to the corresponding flip-flop's O output. All outputs  
will be forced LOW independently of Clock or Data inputs by a  
LOW voltage level on the MR input.  
• Industrial operating temperature range: –40°C to +85°C  
• Packages available:  
– 20-pin173milwideplasticTSSOP(L)  
– 20-pin300milwideplasticDIP(P)  
– 20-pin150milwideplasticQSOP(Q)  
– 20-pin150milwideplasticTQSOP(R)  
– 20-pin300milwideplasticSOIC(S)  
Device models available upon request.  
Logic Block Diagram  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
CP  
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
MR  
O
0
O1  
O2  
O3  
O4  
O5  
O
6
O7  
Truth Table(1)  
Product Pin Configuration  
Product Pin Description  
Inputs  
Outputs  
Pin Name  
MR  
Description  
Mode  
MR  
CP  
X
↑
DN  
X
h
ON  
L
Master Reset (Active LOW)  
MR  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
1
2
3
4
5
6
7
8
9
10  
20 Vcc  
19 O7  
18 D7  
Reset (Clear)  
Load "1"  
Load "0"  
L
H
H
CP  
Clock Pulse Input  
(Active Rising Edge)  
20-PIN  
L20  
P20  
Q20  
R20  
S20  
H
D6  
O6  
O5  
D5  
D4  
O4  
CP  
17  
16  
15  
14  
13  
12  
11  
D0-D7  
O0-O7  
GND  
VCC  
Data Inputs  
Data Outputs  
Ground  
↑
l
L
1. H = High Voltage Level  
h = High Voltage Level one setup time  
prior to the LOW-to-HIGH Clock  
transition  
Power  
GND  
L = Low Voltage Level  
l = LOW Voltage Level one setup time  
prior to the LOW-to-HIGH Clock  
Transition  
X = Don’t Care  
↑ = LOW-to-HIGH Clock Transition  
PS2013A 03/09/96  
1
1234

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