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PI6C485311 PDF预览

PI6C485311

更新时间: 2024-10-01 01:20:11
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
6页 370K
描述
3.3V Low Skew 1-to-2 Differential to LVPECL Fanout Buffer

PI6C485311 数据手册

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PI6C485311  
3.3V Low Skew 1-to-2  
Differential to LVPECL Fanout Buffer  
Description  
Features  
Pin-to-pin compatible to ICS85311  
The PI6C485311 is a high-performance low-skew LVPECLfanout  
buffer. PI6C485311 features two selectable differential inputs and  
translates to four LVPECL ultra-low jitter outputs. The inputs  
can also be congured to single-ended with external resistor bias  
circuit. The CLK input accepts LPECL or LVDS or LVHSTL or  
SSTLor HCSLsignals, and PCLK input accepts LVPECLor SSTL  
or CML signals. PI6C485311 is ideal for differential to LVPECL  
translations and/or LVPECL clock distribution. Typical clock  
translation and distribution applications are data-communications  
and telecommunications.  
Maximum operation frequency: 800MHz  
2 pair of differential LVPECL outputs  
CLK, CLK pair accepts LVDS, LVPECL, LVHSTL,  
n
SSTL and HCSL input level  
Output Skew: 100ps (maximum)  
Part-to-part skew: 150ps (maximum)  
Propagation delay: 2ns (maximum)  
3.3V power supply  
o
o
Operating Temperature: -40 C to 85 C  
Packaging (Pb-free & Green avaliable):  
- 8-pin SOIC (W)  
Block Diagram  
Pin Diagram  
Q0  
nQ0  
1
2
3
4
V
8
7
6
5
Q0  
nQ0  
Q1  
CC  
CLK  
CLK  
nCLK  
nCLK  
Q1  
nQ1  
V
EE  
nQ1  
PS8865D  
11/14/06  
1
06-0283  

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