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PCA9506DGG

更新时间： 2024-02-17 18:49:54

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
30页	163K
描述
40-bit I2C-bus I/O port with RESET, OE, and INT

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PCA9506DGG 数据手册

PCA9506

40-bit I²C-bus I/O port with RESET, OE, and INT

Rev. 01 — 14 February 2006

Product data sheet

1. General description

The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I²C-bus

applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable

of sourcing 10 mA and sinking 25 mA with a total package load of 800 mA to allow direct

driving of 40 LEDs. Any of the 40 I/O ports can be conﬁgured as an input or output. Output

ports are totem-pole and their logic state changes at the Acknowledge (bank change).

The device can be conﬁgured to have each input port to be masked in order to prevent it

from generating interrupts when its state changes and to have the I/O data logic state to

be inverted when read by the system master.

An open-drain interrupt (INT) output pin allows monitoring of the input pins and is

asserted each time a change occurs in one or several input ports (unless masked).

The Output Enable (OE) pin 3-states any I/O selected as output and can be used as an

input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).

The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os

as inputs. Three address select pins conﬁgure one of 8 slave addresses.

The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is speciﬁed over

the −40 °C to +85 °C industrial temperature range.

2. Features

■ Standard mode (100 kHz) and Fast mode (400 kHz) compatible I²C-bus serial

interface

■ 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

■ 40 conﬁgurable I/O pins that default to inputs at power-up

■ Outputs:

◆ Totem-pole (10 mA source, 25 mA sink) with controlled edge rate output structure

◆ Active LOW output enable (OE) input pin 3-states all outputs

◆ Output state change on Acknowledge

■ Inputs:

◆ Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level

change of pins programmed as inputs

◆ Programmable Interrupt Mask Control for input pins that do not require an interrupt

when their states change

◆ Polarity Inversion register allows inversion of the polarity of the I/O pins when read

■ Active LOW reset (RESET) input pin resets device to power-up default state

■ 3 programmable address pins allowing 8 devices on the same bus

12 3 4 5 6 7...30

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