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PDU54SERIES

更新时间： 2024-01-09 20:19:27
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4-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE

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PDU54SERIES 数据手册

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PDU54  
Ò
4-BIT, ECL-INTERFACED  
PROGRAMMABLE DELAY LINE  
(SERIES PDU54)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
OUT  
N/C  
N/C  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
IN  
N/C  
N/C  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
IN  
1
N/C  
VEE  
A3  
N/C  
N/C  
A2  
A1  
VEE  
A0  
N/C  
VEE  
A3  
·
·
·
·
·
Digitally programmable in 16 delay steps  
Monotonic delay-versus-address variation  
Precise and stable delays  
Input & outputs fully 100K-ECL interfaced & buffered  
Available in 24-pin DIP (600 mil) socket or SMD  
2
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
OUT  
N/C  
N/C  
3
4
N/C  
N/C  
A2  
5
6
7
9
A1  
8
10  
11  
12  
VEE  
A0  
9
N/C  
N/C  
10  
11  
12  
N/C  
N/C  
PDU54-xx DIP  
PDU54-xxM Military DIP  
PDU54-xxC4 SMD  
PDU54-xxMC4 Mil SMD  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PDU54-series device is a 4-bit digitally programmable delay line.  
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends  
on the address code (A3-A0) according to the following formula:  
IN  
Signal Input  
OUT Signal Output  
A3-A0 Address Bits  
VEE -5 Volts  
TDA = TD0 + TINC * A  
GND Ground  
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of  
the device. The incremental delay is specified by the dash number of the device and can range from  
100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal  
operation.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
Part  
Number  
Incremental Delay  
Per Step (ps)  
100 ± 50  
Total Delay  
Change (ns)  
1.50  
·
Total programmed delay tolerance: 5% or 40ps,  
whichever is greater  
PDU54-100  
PDU54-200  
PDU54-250  
PDU54-400  
PDU54-500  
PDU54-750  
PDU54-1000  
PDU54-1200  
PDU54-1500  
PDU54-2000  
PDU54-2500  
PDU54-3000  
·
·
·
·
·
·
·
Inherent delay (TD0): 3.3ns typical  
Address to input setup (TAIS): 2.9ns  
Operating temperature: 0° to 85° C  
Temperature coefficient: 100PPM/°C (excludes TD0)  
Supply voltage VEE: -5VDC ± 0.7V  
Power Supply Current: -300ma typical (50W to -2V)  
Minimum pulse width: 3ns or 10% of total delay,  
whichever is greater  
3.00  
3.75  
6.00  
7.50  
11.25  
15.00  
18.00  
22.50  
200 ± 60  
250 ± 60  
400 ± 80  
500 ± 100  
750 ± 100  
1000 ± 200  
1200 ± 200  
1500 ± 200  
2000 ± 400  
2500 ± 400  
3000 ± 500  
30.00  
37.50  
45.00  
·
Minimum period: 8ns or 2 x pulse width, whichever  
is greater  
NOTE: Any dash number between 100 and 3000  
not shown is also available.  
A3-A0  
IN  
A i-1  
Ai  
PWIN  
TOAX  
TAIS  
TDA  
PWOUT  
OUT  
Figure 1: Timing Diagram  
Ó1997 Data Delay Devices  
Doc #98004  
3/18/98  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

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