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PDSP16488C0

更新时间： 2024-02-24 22:06:53
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
33页 414K
描述
Single Chip 2D Convolver with Integral Line Delays

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中文翻译

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PDSP16488C0 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PGA, PGA84,13X13Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：S-XPGA-P84
JESD-609代码：e0端子数量：84
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC封装代码：PGA
封装等效代码：PGA84,13X13封装形状：SQUARE
封装形式：GRID ARRAY电源：5 V
认证状态：Not Qualified子类别：DSP Peripherals
标称供电电压：5 V表面贴装：NO
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULARuPs/uCs/外围集成电路类型：GRAPHICS PROCESSOR
Base Number Matches：1

PDSP16488C0 数据手册

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PDSP16488A  
Single Chip 2D Convolver with Integral Line Delays  
Advance Information  
Supersedes version in 1996 Media IC Handbook, HB4599-1.0  
DS3713 - 6.4 December 1997  
and the PDSP16488A MA data sheet, DS3742  
The PDSP16488A is a fully integrated, application specific,  
image processing device. It performs a two dimensional convo-  
lution between the pixels within a video window and a set of  
stored coefficients. An internal multiplier accumulator array can  
be multi-cycled at double or quadruple the pixel clock rate. This  
then gives the window size options listed in Table 1.  
An internal 32kbit RAM can be configured to provide either  
four or eight line delays. The length of each delay can be  
programmed to the users requirement, up to a maximum of 1024  
pixels per line. The line delays are arranged in two groups,which  
may be internally connected in series or may be configured to  
accept separate pixel inputs. This allows interlaced video or  
frame to frame operations to be supported.  
POWER  
EPROM  
COMPOSITE  
DATA  
PIXEL  
CLOCK  
GEN  
ON  
ADDR DATA  
RESET  
CLK  
HRES  
RES  
DELOP  
SYNC  
DELAYED  
SYNC  
EXTRACT  
SYNC  
BYPASS  
ODD FIELD  
PDSP16488A  
OUTPUT  
DATA  
ADC  
L7:0  
D15:0  
OPTIONAL  
FIELD  
DELAY  
The 8-bit coefficients are also stored internally and can be  
downloaded from a host computer or from an EPROM. No  
additional logic is required to support the EPROM and a single  
device can support up to 16 convolvers.  
IP7:0  
The PDSP16488A contains an expansion adder and delay  
network which allows several devices to be cascaded. Con-  
volvers with larger windows can then be fabricated as shown in  
Table 2.  
Intermediate 32-bit precision is provided to avoid any danger  
of overflow, but the final result will not normally occupy all bits.  
The PDSP16488A thus provides a gain control block in the  
output path, which allows the user to align the result to the most  
significant end of the 32-bit word.  
Fig. 1 Typical stand-alone real time system  
FEATURES  
■ The PDSP16488A is a replacement for the  
PDSP16488 (see Note below)  
■ 8 or 16-bit Pixels with rates up to 40 MHz  
■ Window Sizes up to 838 with a Single Device  
■ Eight Internal Line Delays  
■ Supports Interlace and Frame-to-Frame Operations  
■ Coefficients Supplied from an EPROM or Remote Host  
■ Expandable in both X and Y for Larger Windows  
■ Gain Control and Pixel Output Manipulation  
■ 84-pin PGA or 132-pin QFP Package Options  
Window size  
Pixel  
size  
Maximum pixel  
rate (MHz)  
Line delays  
Width  
Depth  
8
8
8
16  
16  
4
8
8
4
8
4
4
8
4
4
20  
20  
10  
20  
10  
431024  
431024  
83512  
43512  
43512  
Note: PDSP16488A devices are not guaranteed to cascade with  
PDSP16488 devices. Mitel Semiconductor do not recommend  
that PDSP16488A be mixed with PDSP16488 devices in a single  
equipment design. The PDSP16488A requires external pullup  
resistors in EPROM Mode (see Static Electrical Characteristics).  
Table 1 Single PDSP16488A configurations  
Max.  
No. of PDSP16488As for N3N window size  
ORDERING INFORMATION  
Commercial (0°C to 170°C)  
PDSP16488A / C0 / AC (PGA)  
Industrial (240°C to 185°C)  
PDSP16488A / B0 / AC (PGA)  
PDSP16488A / B0 / GC (QFP)  
Military (255°C to 1125°C)  
PDSP16488A / A0 / AC (PGA)  
pixel Pixel  
rate size  
(MHz)  
333  
535 737 939 11311 15315 23323  
10  
10  
20  
20  
40  
40  
9
-
-
-
-
8
16  
8
16  
8
1
1
1
1
1
2
1
2
2
4
1
2
2
4
4
-
6
-
-
-
4
-
6
-
-
-
4
-
8
-
-
-
PDSP16488A / A0 / GC (QFP)  
4* 4*  
-
PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B*  
PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B*  
*See Notes following Static Electrical CharacteristicsTable  
-
16  
-
*Maximum rate is limited to 30MHz by line store expansion delays  
Table 2 PDSP16488As needed to implement typical window sizes  
1234567...33

中文翻译

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