Datasheet > PCX7457VG550NC

PCX7457VG550NC

更新时间： 2023-01-02 15:58:10

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
60页	917K
描述
RISC Microprocessor, 32-Bit, 550MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483

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PCX7457VG550NC 数据手册

PC7457

– Instruction cache can provide four instructions per clock cycle; data cache can

provide four words per clock cycle

– Caches can be disabled in software

– Caches can be locked in software

– MESI data cache coherency maintained in hardware

– Separate copy of data cache tags for efficient snooping

– Parity support on cache and tags

– No snooping of instruction cache except for icbi instruction

– Data cache supports AltiVec LRU and transient instructions

– Critical double- and/or quad-word forwarding is performed as needed. Critical quad-

word forwarding is used for AltiVec loads and instruction fetches. Other accesses

use critical double-word forwarding

• Level 2 (L2) cache interface

– On-chip, 512 Kbyte, eight-way set-associative unified instruction and data cache

– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

– A total nine-cycle load latency for an L1 data cache miss that hits in L2

– PLRU replacement algorithm

– Cache write-back or write-through operation programmable on a per-page or per-

block basis

– 64-byte, two-sectored line size

– Parity support on cache

• Level 3 (L3) cache interface (not implemented on PC7447)

– Provides critical double-word forwarding to the requesting unit

– Internal L3 cache controller and tags

– External data SRAMs

– Support for 1, 2, and 4M bytes (MB) total SRAM space

– Support for 1 or 2 MB of cache space

– Cache write-back or write-through operation programmable on a per-page or per-

block basis

– 64-byte (1 MB) or 128-byte (2 MB) sectored line size

– Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a

total of 1-, 2-, or 4-MB of private memory

– Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined

synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous

Burst SRAMs

– Supports parity on cache and tags

– Configurable core-to-L3 frequency divisors

– 64-bit external L3 data bus sustains 64-bit per L3 clock cycle

• Separate memory management units (MMUs) for Instructions and data

– 52-bit virtual address; 32- or 36-bit physical address

– Address translation for 4 Kbyte pages, variable-sized blocks, and 256M bytes

segments

5345D–HIREL–07/06

1...4 5 678 9 10...60

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与PCX7457VG550NC相关器件

型号	品牌	描述	获取价格	数据表
PCX7457VG600NC	ATMEL	RISC Microprocessor, 32-Bit, 600MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格
PCX7457VG650NC	ATMEL	RISC Microprocessor, 32-Bit, 650MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格
PCX7457VG666NC	ATMEL	RISC Microprocessor, 32-Bit, 666MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格
PCX7457VG700NC	ATMEL	RISC Microprocessor, 32-Bit, 700MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格
PCX7457VG866NC	ATMEL	RISC Microprocessor, 32-Bit, 866MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格
PCX7457VGH1000NC	ATMEL	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格

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