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PCA9536DP PDF预览

PCA9536DP

更新时间: 2024-01-28 11:13:05
品牌 Logo 应用领域
恩智浦 - NXP 并行IO端口微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
16页 157K
描述
4-bit I2C and SMBus I/O port

PCA9536DP 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA, BGA8,2X4,20针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
JESD-30 代码:R-XBGA-B8JESD-609代码:e1
长度:1.98 mm湿度敏感等级:1
位数:4I/O 线路数量:4
端口数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:VFBGA
封装等效代码:BGA8,2X4,20封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:0.5 mm子类别:Parallel IO Ports
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.9 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9536DP 数据手册

 浏览型号PCA9536DP的Datasheet PDF文件第2页浏览型号PCA9536DP的Datasheet PDF文件第3页浏览型号PCA9536DP的Datasheet PDF文件第4页浏览型号PCA9536DP的Datasheet PDF文件第6页浏览型号PCA9536DP的Datasheet PDF文件第7页浏览型号PCA9536DP的Datasheet PDF文件第8页 
Philips Semiconductors  
Objective data sheet  
4-bit I2C and SMBus I/O port  
PCA9536  
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O3  
DATA FROM  
SHIFT REGISTER  
OUTPUT PORT  
REGISTER DATA  
CONFIGURATION  
REGISTER  
V
DD  
DATA FROM  
SHIFT REGISTER  
Q
D
Q1  
FF  
100 k  
ESD PROTECTION DIODE  
WRITE  
CONFIGURATION  
PULSE  
D
C
Q
Q
Q
C
K
FF  
I/O0 TO I/O3  
WRITE PULSE  
K
Q2  
OUTPUT  
PORT  
ESD PROTECTION DIODE  
REGISTER  
V
SS  
INPUT PORT  
REGISTER  
D
Q
INPUT PORT  
REGISTER DATA  
FF  
READ PULSE  
Q
C
K
DATA FROM  
SHIFT REGISTER  
POLARITY  
REGISTER DATA  
D
Q
Q
FF  
WRITE  
POLARITY  
PULSE  
C
K
POLARITY  
INVERSION  
REGISTER  
SW02192  
NOTE: At Power-on Reset, all registers return to default values.  
Figure 3. Simplified schematic of I/O0 to I/O3  
I/O port  
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up (100 ktyp.) to V . The  
DD  
input voltage may be raised above V to a maximum of 5.5 V.  
DD  
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be  
exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and  
either V or V  
.
SS  
DD  
5
2004 Aug 20  

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