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PCA6107 PDF预览

PCA6107

更新时间： 2024-02-24 22:28:06
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
24页 307K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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PCA6107 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOIC-18针数：18
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.37
Is Samacsys：NJESD-30 代码：R-PDSO-G18
长度：11.55 mm位数：8
I/O 线路数量：8端口数量：1
端子数量：18最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP18,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Parallel IO Port
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA6107 数据手册

 浏览型号PCA6107的Datasheet PDF文件第2页浏览型号PCA6107的Datasheet PDF文件第3页浏览型号PCA6107的Datasheet PDF文件第4页浏览型号PCA6107的Datasheet PDF文件第6页浏览型号PCA6107的Datasheet PDF文件第7页浏览型号PCA6107的Datasheet PDF文件第8页 
PCA6107  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS139B–JANUARY 2006–REVISED OCTOBER 2006  
SIMPLIFIED SCHEMATIC OF P1 TO P7  
Data From  
Shift Register  
Output Port  
Register Data  
Configuration  
Register  
V
CC  
Data From  
Shift Register  
Q
D
FF  
Write Configuration  
Pulse  
D
Q
C
K
Q
FF  
P1 to P7  
Write Pulse  
C
K
Q
ESD Protection Diode  
Output  
Port  
Register  
Input  
Port  
GND  
Register  
Input Port  
Register Data  
D
Q
FF  
Read Pulse  
C
K
Q
Data From  
Shift Register  
Polarity  
Register Data  
D
Q
FF  
Write Polarity Pulse  
C
K
Q
Polarity  
Inversion  
Register  
A. On power up or reset, all registers return to default values.  
I2C Interface  
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be  
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data  
transfer may be initiated only when the bus is not busy.  
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on  
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address  
byte is sent, MSB first, including the data direction bit (R/W).  
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA  
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device  
must not be changed between the Start and the Stop conditions.  
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control  
commands (Start or Stop) (see Figure 2).  
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the  
master (see Figure 1).  
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop  
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before  
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK  
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see  
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,  
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold  
times must be met to ensure proper operation.  
5
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