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PAC-POWR1208

更新时间： 2024-09-29 21:55:43

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
6页	992K
描述
ispPAC-POWR1208 Evaluation Board

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PAC-POWR1208 数据手册

ispPAC-POWR1208 Evaluation Board

PAC-POWR1208-EV

April 2004

Application Note AN6040

Introduction

The Lattice Semiconductor ispPAC^®-POWR1208 In-System-Programmable Analog Circuit allows designers to

implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a

single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET

drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208 provides the

power-supply designer with a rich set of features in a single device.

ISP™ (In-System-Programmability) provides the designer with an unprecedented level of ﬂexibility, allowing him to

conﬁgure analog parameters such as threshold voltages as well as deﬁning state machines and combinatorial logic

functions. All conﬁguration data is stored internally in E²CMOS^®nonvolatile memory. Programming a conﬁguration

is accomplished through an industry-standard JTAG IEEE 1149.1 interface.

PAC-POWR1208-EV Evaluation Board

The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly conﬁgure and evaluate the isp-

PAC-POWR1208 on a fully assembled printed-circuit board.The double-sided board supports a 44-pin TQFP pack-

age, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user

prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD^®programming cable con-

nected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the isp-

PAC-POWR1208 can be easily conﬁgured using PAC-Designer^®software.

Figure 1. PAC-POWR1208-EV Evaluation Board

www.latticesemi.com

an6040_01

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