Datasheet > P3503EVG

P3503EVG

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
其他 - ETC		晶体晶体管场效应晶体管
页数	文件大小	规格书
5页	141K
描述
P-Channel Logic Level Enhancement Mode Field Effect Transistor

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数据手册

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P3503EVG 数据手册

P3503EVG

SOP-8

NIKO-SEM

P-Channel Logic Level Enhancement

Lead-Free

Mode Field Effect Transistor

DYNAMIC

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge²

Gate-Source Charge²

Gate-Drain Charge²

Turn-On Delay Time²

Rise Time²

C_iss

970

V_GS= 0V, V_DS= -10V, f = 1MHz

C_oss

C_rss

Q_g

370

180

V_DS= 0.5V_(BR)DSS, V_GS= -10V,

I_D= -8A

Q_gs

Q_gd

t_d(on)

t_r

V_DS= -15V, R_L= 1Ω

Turn-Off Delay Time²

Fall Time²

t_d(off)

t_f

I_D@ -1A, V_GS= -10V, R_GS= 6Ω

180

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T_C= 25 °C)

Continuous Current

Pulsed Current³

I_S

-3

-6

-1

I_SM

Forward Voltage¹

V_SD

I_F= -1A, V_GS= 0V

Reverse Recovery Charge

Q_rr

7.9

¹Pulse test : Pulse Width £ 300 msec, Duty Cycle £ 2％.

²Independent of operating temperature.

³Pulse width limited by maximum junction temperature.

REMARK: THE PRODUCT MARKED WITH “P3503EVG”, DATE CODE or LOT #

Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

Jan-06-2005

123 4 5

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