Data Addendum
January 2002
ORCA OR3LxxxB Series FPGAs
Features (continued)
■ Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC† processors with user-configurable
address space provided.
■ Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain drive capability.
■ Parallel readback of configuration data capability with
the built-in microprocessor interface.
■ Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers.Two PCMs are provided
per device.
■ New programmable I/O 3-state FF allows 3-state
buffer control signals to be set up a clock cycle early
for improved clock to output delays.
■ True internal 3-state, bidirectional buses with simple
System-Level Features
control provided by the SLIC.
■ 32 × 4 RAM per PFU, configurable as single- or dual-
port. Create large, fast RAM/ROM blocks (128 × 8 in
only eight PFUs) using the SLIC decoders as bank
drivers.
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA OR3LxxxB include the following:
■ Full PCI local bus compliance for all devices in
3.3 V and 5 V PCI systems. Pin-selectable I/O
clamping diodes provide 3.3 V and 5 V compliance
and 5 V tolerance.
■ Full UTOPIA Level III I/O compliance (6.0 ns
CLK -> OUT, 2.0 ns setup with 0 ns hold).
* i960 is a registered trademark of Intel Corporation.
† PowerPC is a registered trademark of International Business
Machines, Inc.
Table 2. ORCA Series 3L System Performance
Parameter
# PFUs
-7
-8
Unit
16-bit Loadable Up/Down Counter
16-bit Accumulator
2
2
151
151
176
176
MHz
MHz
8 × 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
32 × 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
11.5
8
15
38
93
129
46
116
152
MHz
MHz
MHz
4
4
173
231
209
277
MHz
MHz
128 × 8 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
8
8
151
151
181
181
MHz
MHz
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs6
0.25
0
2.30
1.29
2.00
1.12
ns
ns
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs7
2
0
2
7.97
3.75
7.97
6.84
3.16
6.84
ns
ns
ns
36-bit Parity Check (internal)
1. Implemented using 8 × 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 × 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 × 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain
only pipelining registers).
4. Implemented using 32 × 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 × 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4
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