Datasheet > OR2C40A-2PS432I

OR2C40A-2PS432I

更新时间： 2022-12-15 02:43:32

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Field-Programmable Gate Arrays

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OR2C40A-2PS432I 数据手册

Data Sheet

June 1999

ORCA Series 2 FPGAs

Programmable Logic Cells (continued))

COUT

CARRY

QLUT3

WD3

WD2

REG3

CARRY

SR EN

PFU_NAND

QLUT2

REG2

CARRY

SR EN

PFU_MUX

PFU_XOR

QLUT1

REG1

WD1

WD0

SR EN

CARRY

QLUT0

REG0

SR EN

CIN

LSR

GSR

WD[3:0]

CKEN

TRI

5-4573(F)

Key: C = controlled by configuration RAM.

Figure 3. Simplified PFU Diagram

Figure 2 and Figure 3 show high-level and detailed

views of the ports in the PFU, respectively. The ports

are referenced with a two- to four-character suffix to a

PFU’s location. As mentioned, there are two 5-bit input

data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit

input data bus (WD[3:0]) to the latches/FFs, and an

output data bus (O[4:0]).

found in each PLC are also shown, although they actu-

ally reside external to the PFU.

Each latch/FF can accept data from the LUT. Alterna-

tively, the latches/FFs can accept direct data from

WD[3:0], eliminating the LUT delay if no combinatorial

function is needed. The LUT outputs can bypass the

latches/FFs, which reduces the delay out of the PFU. It

is possible to use the LUT and latches/FFs more or

less independently. For example, the latches/FFs can

be used as a 4-bit shift register, and the LUT can be

used to detect when a register has a particular pattern

in it.

Figure 3 shows the four latches/FFs (REG[3:0]) and the

64-bit look-up table (QLUT[3:0]) in the PFU. The PFU

does combinatorial logic in the LUT and sequential

logic in the latches/FFs. The LUT is static random

access memory (SRAM) and can be used for read/

write or read-only memory. The eight 3-state buffers

Lucent Technologies Inc.

1...3 4 567 8 9...192

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