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OPA621KU PDF预览

OPA621KU

更新时间: 2024-01-17 12:47:26
品牌 Logo 应用领域
BB 运算放大器
页数 文件大小 规格书
16页 195K
描述
Wideband Precision OPERATIONAL AMPLIFIER

OPA621KU 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP8,.3Reach Compliance Code:unknown
风险等级:5.58放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK最大平均偏置电流 (IIB):40 µA
25C 时的最大偏置电流 (IIB):30 µA标称共模抑制比:75 dB
频率补偿:YES (AVCL>=2)最大输入失调电压:1000 µV
JESD-30 代码:R-CDIP-T8JESD-609代码:e0
低-失调:NO标称负供电电压 (Vsup):-5 V
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:+-5 V认证状态:Not Qualified
最小摆率:350 V/us标称压摆率:500 V/us
子类别:Operational Amplifier最大压摆率:30 mA
供电电压上限:7 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:BIPOLAR
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
标称均一增益带宽:500000 kHz最小电压增益:160
Base Number Matches:1

OPA621KU 数据手册

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COMPENSATION  
error band of ±200µV centered around the final value of 2V.  
The OPA621 is stable in inverting gains of –2V/V and in  
non-inverting gains +2V/V. Phase margin for both con-  
figurations is approximately 50°. Inverting and non-invert-  
ing gains of unity should be avoided. The minimum stable  
gains of +2V/V and –2V/V are the most demanding circuit  
configurations for loop stability and oscillations are most  
likely to occur in these gains. If possible, use the device in  
a noise gain greater than three to improve phase margin and  
reduce the susceptibility to oscillation. (Note that, from a  
stability standpoint, an inverting gain of –2V/V is equivalent  
to a noise gain of 3.) Gain and phase response for other gains  
are shown in the Typical Performance Curves.  
Settling time, specified in an inverting gain of two, occurs in  
only 25ns to 0.01% for a 2V step, making the OPA621 one  
of the fastest settling monolithic amplifiers commercially  
available. Settling time increases with closed-loop gain and  
output voltage change as described in the Typical Perform-  
ance Curves. Preserving settling time requires critical  
attention to the details as mentioned under “Wiring Precau-  
tions.” The amplifier also recovers quickly from input  
overloads. Overload recovery time to linear operation from  
a 50% overload is typically only 30ns.  
In practice, settling time measurements on the OPA621  
prove to be very difficult to perform. Accurate measurement  
is next to impossible in all but the very best equipped labs.  
Among other things, a fast flat-top generator and high speed  
oscilloscope are needed. Unfortunately, fast flat-top genera-  
tors, which settle to 0.01% in sufficient time, are scarce and  
expensive. Fast oscilloscopes, however, are more commonly  
available. For best results a sampling oscilloscope is recom-  
mended. Sampling scopes typically have bandwidths that  
are greater than 1GHz and very low capacitance inputs.  
They also exhibit faster settling times in response to signals  
that would tend to overload a real-time oscilloscope.  
The high-frequency response of the OPA621 in a good  
layout is flat with frequency for higher-gain circuits. How-  
ever, low-gain circuits and configurations where large  
feedback resistances are used, can produce high-frequency  
gain peaking. This peaking can be minimized by connecting  
a small capacitor in parallel with the feedback resistor. This  
capacitor compensates for the closed-loop, high frequency,  
transfer function zero that results from the time constant  
formed by the input capacitance of the amplifier (typically  
2pF after PC board mounting), and the input and feedback  
resistors. The selected compensation capacitor may be a  
trimmer, a fixed capacitor, or a planned PC board capaci-  
tance. The capacitance value is strongly dependent on circuit  
layout and closed-loop gain. Using small resistor values will  
preserve the phase margin and avoid peaking by keeping the  
break frequency of this zero sufficiently high. When high  
closed-loop gains are required, a three-resistor attenuator  
(tee network) is recommended to avoid using large value  
resistors with large time constants.  
Figure 7 shows the test circuit used to measure settling time  
for the OPA621. This approach uses a 16-bit sampling  
oscilloscope to monitor the input and output pulses. These  
waveforms are captured by the sampling scope, averaged,  
and then subtracted from each other in software to produce  
the error signal. This technique eliminates the need for the  
traditional “false-summing junction,” which adds extra  
parasitic capacitance. Note that instead of an additional flat-  
top generator, this technique uses the scope’s built-in cali-  
bration source as the input signal.  
SETTLING TIME  
Settling time is defined as the total time required, from the  
input signal step, for the output to settle to within the  
specified error band around the final value. This error band  
is expressed as a percentage of the value of the output  
transition, a 2V step. Thus, settling time to 0.01% requires an  
DIFFERENTIAL GAIN AND PHASE  
Differential Gain (DG) and Differential Phase (DP) are  
among the more important specifications for video applica-  
tions. DG is defined as the percent change in closed-loop  
gain over a specified change in output voltage level. DP is  
1pF to 4pF (Adjust for Optimum Settling)  
0 to +2V, f = 1.25MHz  
VIN  
100  
200Ω  
+5VDC  
0 to –2V  
VOUT  
OPA621  
NOTE: Test fixture built using all surface-mount components. Ground  
plane used on component side and entire fixture enclosed in metal case.  
Both power supplies bypassed with 10µF Tantalum || 0.01µF ceramic  
capacitors. It is directly connected (without cable) to TIME CAL trigger  
source on Sampling Scope (Data Precision's Data 6100 with Model  
640-1 plug-in). Input monitored with Active Probe (Channel 1).  
200Ω  
To Active Probe (Channel 2)  
on sampling scope.  
–5VDC  
FIGURE 7. Settling Time Test Circuit.  
®
13  
OPA621  

OPA621KU 替代型号

型号 品牌 替代类型 描述 数据表
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