Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> ONET3301PARGTR

ONET3301PARGTR

更新时间： 2024-02-08 23:09:55

品牌	Logo	应用领域
德州仪器 - TI		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路放大器异步传输模式
页数	文件大小	规格书
12页	254K
描述
155-MBPS TO 3.3-GBPS LIMITING AMPLIFIER

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ONET3301PARGTR 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	3 X 3 MM, 0.50 MM PITCH, GREEN, PLASTIC, QFN-16	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.23
Is Samacsys：	N	应用程序：	SONET;SDH
JESD-30 代码：	S-PQCC-N16	JESD-609代码：	e4
长度：	3 mm	湿度敏感等级：	2
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装等效代码：	LCC16,.12SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.04 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm	Base Number Matches：	1

ONET3301PARGTR 数据手册

ꢀꢁ ꢂꢃ ꢄ ꢄ ꢅꢆ ꢇꢈ

ꢆꢉ ꢉꢊꢋ ꢌ ꢍ ꢎ ꢃꢀ ꢄ ꢏ ꢄ ꢊꢐꢌꢍ ꢎ ꢑꢒ ꢋ ꢒ ꢃꢒ ꢁꢐ ꢈꢋ ꢇꢑꢒ ꢓ ꢒꢂꢔ

SLLS603B − MARCH 2004 − REVISED DECEMBER 2004

block diagram

A simplified block diagram of the ONET3301PA is shown in Figure 1.

This compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation

block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation

block.

The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.

COC2 COC1

VCC

Offset

Cancellation

GND

OUTPOL

VCCO

DIN+

DIN−

DOUT+

−

DOUT−

CML

Output

Buffer

Input Buffer

Gain Stage

DISABLE

Bandgap Voltage

Reference and

Bias Current

Generation

Loss of Signal

and

RSSI Detection

LOS

RSSI

Figure 1. Block Diagram

high-speed data path

The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data

path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide

the required typical gain of about 50 dB and a CML output stage. The amplified data output signal is available

at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also

includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,

controlled by the signal applied to the DISABLE input pin.

An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even

for small input data signals.

The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.

For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be

connected to the COC1/COC2 pins.

loss of signal and RSSI detection

The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block

a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This

signal is available at the RSSI output pin.

Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means

of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of

signal is indicated at the LOS pin.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

123 4 5 6 7...12

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